Re: [SeaBIOS] [PATCH v2 0/4] support booting more than 255 CPUs with QEMU

On Mon, 20 Jun 2016 13:51:28 +0200 Gerd Hoffmann wrote: > Hi, > > > I need to dust RFC off and respin as Paolo wanted to sync APIC ID > > other way than in RFC and also on list there is v2 ACPI refactoring > > that x2APIC enablement depends on. > > Soft freeze is only one

[SeaBIOS] [PATCH v3] fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL

OS usually expects BIOS to set certain bits in MSR_IA32_FEATURE_CONTROL for some features (e.g. VMX and LMCE). QEMU provides a fw_cfg file "etc/msr_feature_control" to advise bits that should be set in MSR_IA32_FEATURE_CONTROL. If this file exists, SeaBIOS will set the advised bits in that MSR.