> On Thu, Jul 07, 2016 at 04:00:40PM +0200, Paolo Bonzini wrote:
> > Currently the MTRRs and MSR_IA32_FEATURE_CONTROL are not restored on S3
> > resume. Because these have to be applied to all processors, SMP setup
> > has to be added to S3 resume.
> >
> > There are two differences between the
On Thu, Jul 07, 2016 at 04:00:40PM +0200, Paolo Bonzini wrote:
> Currently the MTRRs and MSR_IA32_FEATURE_CONTROL are not restored on S3
> resume. Because these have to be applied to all processors, SMP setup
> has to be added to S3 resume.
>
> There are two differences between the boot and
On Mon, Jul 04, 2016 at 12:41:14PM -0400, Kevin O'Connor wrote:
> The original "lgpl vgabios" had a special case for dh==0xff in its
> int1013 (write string) code. There does not appear to be any VGABIOS
> documentation supporting this as an externally available feature. It
> appears this was
Currently the MTRRs and MSR_IA32_FEATURE_CONTROL are not restored on S3
resume. Because these have to be applied to all processors, SMP setup
has to be added to S3 resume.
There are two differences between the boot and resume paths. First,
romfile_* is not usable in the resume paths so we move
On 07/07/16 14:12, Paolo Bonzini wrote:
>
>> I've worried that if I only *call* these interfaces to set the MSR, then
>> the next (independent) use of the same interfaces would clear the MSR
>> through the INIT-SIPI-SIPI. That would have forced me to modify the
>> protocol / PPI implementations
> I've worried that if I only *call* these interfaces to set the MSR, then
> the next (independent) use of the same interfaces would clear the MSR
> through the INIT-SIPI-SIPI. That would have forced me to modify the
> protocol / PPI implementations so that any use of them would reprogram
> the
