[SeaBIOS] Re: [PATCH] limit address space used for pci devices, part two

address space limits. > > Signed-off-by: Gerd Hoffmann Reviewed-by: Igor Mammedov > --- > src/fw/pciinit.c | 15 ++- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c > index bb44dc296047..b3e359d7

[SeaBIOS] Re: [PATCH v2 4/4] only enable 64bit pci io window when RAM >64G

On Fri, 21 Jun 2024 14:05:17 +0200 Gerd Hoffmann wrote: > On Wed, Jun 19, 2024 at 11:21:14AM GMT, John Levon wrote: > > Older 32-bit Linux VMs (including Ubuntu 16.10) have issues with the > > 64-bit pci io window, failing during boot with errors like: > > Well. Why people would use *that*

[SeaBIOS] Re: [PATCH 4/4] only enable 64bit pci io window when RAM >60G

On Thu, 20 Jun 2024 15:43:33 +0100 John Levon wrote: > On Thu, Jun 20, 2024 at 04:00:05PM +0200, Igor Mammedov wrote: > > > Regardless of which way is chosen some users will suffer one way or another. > > My vote would be to keep current behavior so 'modern' guests would

[SeaBIOS] Re: [PATCH v2 4/4] only enable 64bit pci io window when RAM >64G

On Wed, 19 Jun 2024 11:21:14 +0100 John Levon wrote: > Older 32-bit Linux VMs (including Ubuntu 16.10) have issues with the > 64-bit pci io window, failing during boot with errors like: > > virtio_balloon virtio2: virtio: device uses modern interface but does not > have

[SeaBIOS] Re: [PATCH 4/4] only enable 64bit pci io window when RAM >60G

On Mon, 17 Jun 2024 16:04:29 +0200 Gerd Hoffmann wrote: > Hi, > > > While it's possible to tweak MMIO windows size on QEMU CLI, > > it's inconvenient and that cascades over to upper layers > > (libvirt, whatnot on top of that) eventually ending up at > > end-user somewhere if that config

[SeaBIOS] Re: [PATCH 4/4] only enable 64bit pci io window when RAM >60G

On Mon, 17 Jun 2024 13:42:20 +0200 Gerd Hoffmann wrote: > On Fri, Jun 14, 2024 at 01:05:44PM GMT, Kevin O'Connor wrote: > > On Fri, Jun 14, 2024 at 12:54:28PM +0200, Gerd Hoffmann wrote: > > > Hi, > > > > > > > Be a bit more conservative, and only enable the window by default when > > > >

[SeaBIOS] Re: an issue with win10 boot and different compiler versions

On Tue, 20 Feb 2024 14:41:50 -0500 Kevin O'Connor wrote: > On Sat, Feb 10, 2024 at 11:17:54PM +0300, Michael Tokarev wrote: > > So.. the difference is vgabios only, not seabios (vgabios-stdvga in this > > case). > > > > And I can't get it to work with debugging vgabios, it always fails even >

[SeaBIOS] Re: [PATCH] qemu: disable builtin acpi and smbios tables by default.

ether at some point in the future. > > Signed-off-by: Gerd Hoffmann Reviewed-by: Igor Mammedov > --- > src/Kconfig | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/src/Kconfig b/src/Kconfig > index 3a8ffa15fded..83ddf45143c3 100644 > --- a/

[SeaBIOS] Re: [PATCH 0/2] improve ZoneHigh memory management

On Thu, 21 Apr 2022 11:33:24 +0200 Gerd Hoffmann wrote: > When running out of memory get a chunk of memory from ZoneTmpHigh to > > expand ZoneHigh. Drop simliar logic fro pmm code because it's not > > needed ay more. > > > > This fixes some scalability problems, for example with lots of

[SeaBIOS] Re: [PATCH] MP: fix mptable interrupt source generation for pci devices

On Wed, 20 Apr 2022 13:32:33 +0200 Paul Menzel wrote: > Dear Igor, dear Kevin, dear Gerd, > > > Am 20.04.22 um 11:14 schrieb Igor Mammedov: > > On Tue, 19 Apr 2022 09:52:42 -0400 Kevin O'Connor wrote: > > > >> On Tue, Apr 19, 2022 at 11:46:59AM +0200, Ge

[SeaBIOS] Re: [PATCH] MP: fix mptable interrupt source generation for pci devices

On Tue, 19 Apr 2022 09:52:42 -0400 Kevin O'Connor wrote: > On Tue, Apr 19, 2022 at 11:46:59AM +0200, Gerd Hoffmann wrote: > > > > diff --git a/src/fw/mptable.c b/src/fw/mptable.c > > > > index 47385cc..3a7b02f 100644 > > > > --- a/src/fw/mptable.c > > > > +++ b/src/fw/mptable.c > > > > > > If

[SeaBIOS] Re: MP tables do not report multiple CPUs in Qemu 6.2.0 on x86 when given -smp cpus=n flag

On Wed, 19 Jan 2022 15:48:20 + Peter Maydell wrote: > On Wed, 19 Jan 2022 at 14:44, Godmar Back wrote: > > after upgrading to 6.2.0, I observed that code such as MIT's xv6 (see > > [1]) is no longer able to detect multiple CPUs. Their code works in > > 6.1.1, however. > > Hi; this isn't

[SeaBIOS] Re: MP tables do not report multiple CPUs in Qemu 6.2.0 on x86 when given -smp cpus=n flag

On Thu, 20 Jan 2022 09:46:09 -0500 Godmar Back wrote: > [this is a follow-up email; I took qemu-discuss and qemu-devel off the > distribution list] > > On Thu, Jan 20, 2022 at 4:04 AM Igor Mammedov wrote: > > > > Legacy MP table is not actively maintained part of

[SeaBIOS] [PATCH v3 2/2] pci: let firmware reserve IO for pcie-pci-bridge

if PCIe hotplug is in use. [1] "pci: reserve resources for pcie-pci-bridge to fix regressed hotplug on q35" [2] Fixes: 76327b9f32a ("fw/pci: do not automatically allocate IO region for PCIe bridges") Signed-off-by: Igor Mammedov imamm...@redhat.com CC: mapfe...@redhat.com CC: kra

[SeaBIOS] [PATCH v3 1/2] pci: reserve resources for pcie-pci-bridge to fix regressed hotplug on q35

it was switched to ACPI based PCI hotplug on Q35 by default at that time. RHBZ: https://bugzilla.redhat.com/show_bug.cgi?id=2001732 [1] Fixes: 3aa31d7d637 ("hw/pci: reserve IO and mem for pci express downstream ports with no devices attached") Signed-off-by: Igor Mammedov imamm...@redhat.com

[SeaBIOS] [PATCH v3 0/2] pci: reserve resources for pcie-pci-bridge to fix regressed hotplug on q35 with ACPI hotplug enabled

capability. Patch [2/2] fixes missed IO reservation, by making sure that in the case of the bridge firmware reserves IO resource. Igor Mammedov (2): pci: reserve resources for pcie-pci-bridge to fix regressed hotplug on q35 pci: let firmware reserve IO for pcie-pci-bridge src/fw/pciinit.c

[SeaBIOS] [PATCH v2] pci: reserve resources for pcie-pci-bridge to fix regressed hotplug on q35 with ACPI hotplug enabled

tream ports with no devices attached") [2] Fixes: 76327b9f32a ("fw/pci: do not automatically allocate IO region for PCIe bridges") Signed-off-by: Igor Mammedov CC: mapfe...@redhat.com CC: kra...@redhat.com CC: m...@redhat.com CC: lviv...@redhat.com CC: jus...@redhat.com --- s

[SeaBIOS] Re: [PATCH] pci: reserve resources for pcie-pci-bridge to fix regressed hotplug on q35 with ACPI hotplug enabled

On Sat, 27 Nov 2021 11:19:35 +0100 Paul Menzel wrote: > Dear Igor, > > > Am 26.11.21 um 19:46 schrieb Igor Mammedov: > > hotplug of a PCI device to empty at startup pcie-pci-bridge fails when > > “to empty”, what does that mean? meaning is pcie-pci-bridge that d

[SeaBIOS] [PATCH] pci: reserve resources for pcie-pci-bridge to fix regressed hotplug on q35 with ACPI hotplug enabled

") [2] Fixes: 76327b9f32a ("fw/pci: do not automatically allocate IO region for PCIe bridges") Signed-off-by: Igor Mammedov CC: mapfe...@redhat.com CC: kra...@redhat.com CC: m...@redhat.com CC: lviv...@redhat.com CC: jus...@redhat.com --- s

[SeaBIOS] Re: [PATCH] acpi: add xsdt support

On Fri, 27 Mar 2020 09:24:10 +0100 Gerd Hoffmann wrote: > In case a xsdt table is present (and located below 4G) > prefer it over rsdt. not related to this patch, but in connection to supporting HW reduced profile, check places that use FADT. i.e. * check for newer FADT revision * skip pm

Re: [SeaBIOS] Saving a few bytes across a reboot

On Wed, 7 Feb 2018 08:51:58 -0500 Stefan Berger wrote: > On 01/10/2018 08:22 AM, Laszlo Ersek wrote: > > Stefan, > > > > On 01/09/18 20:02, Stefan Berger wrote: > > [...] > So the point is SMM is needed for UEFI. QEMU would need to provide the > ACPI code for

Re: [SeaBIOS] Saving a few bytes across a reboot

On Thu, 11 Jan 2018 09:29:14 -0500 Stefan Berger <stef...@linux.vnet.ibm.com> wrote: > On 01/11/2018 09:02 AM, Laszlo Ersek wrote: > > On 01/11/18 13:40, Igor Mammedov wrote: > >> On Wed, 10 Jan 2018 17:45:52 +0100 > >> Laszlo Ersek <ler...@redhat.c

Re: [SeaBIOS] Saving a few bytes across a reboot

On Wed, 10 Jan 2018 17:45:52 +0100 Laszlo Ersek wrote: > On 01/10/18 16:19, Marc-André Lureau wrote: > > Hi > > > > - Original Message - > >> > >> BTW, from the "TCG PC Client Platform TPM Profile (PTP) > >> Specification", it seems like the FIFO (TIS) interface is

Re: [SeaBIOS] [Qemu-devel] allocation zone extensions for the firmware linker/loader

On Sat, 3 Jun 2017 09:36:23 +0200 Laszlo Ersek wrote: > On 06/02/17 17:45, Laszlo Ersek wrote: > > > The patches can cause linker/loader breakage when old firmware is booted > > on new QEMU. However, that's no problem (it's nothing new), the next > > release of QEMU should

Re: [SeaBIOS] [Qemu-devel] Minimum RAM size for PC machines?

On Wed, 22 Mar 2017 11:03:44 +0100 Thomas Huth wrote: > On 22.03.2017 10:08, Markus Armbruster wrote: > [...] > > Are we now ready to accept a simple & stupid patch that actually helps > > users, say letting boards that care declare minimum and maximum RAM > > size? And make

Re: [SeaBIOS] [PATCH v7 5/5] QEMU fw_cfg: Write fw_cfg back on S3 resume

<b...@skyportsystems.com> > Reviewed-by: Laszlo Ersek <ler...@redhat.com> Reviewed-by: Igor Mammedov <imamm...@redhat.com> > --- > src/fw/romfile_loader.c | 33 + > src/fw/romfile_loader.h | 2 ++ > src/resume.c| 4

Re: [SeaBIOS] [PATCH v5 4/5] QEMU fw_cfg: Add functions for accessing files by key

, so add simple API to get file 'key' and write to file by using saved at boot time 'key'. + with Laszlo's suggestions on code consolidation Reviewed-by: Igor Mammedov <imamm...@redhat.com> > Signed-off-by: Ben Warren <b...@skyportsystems.com> > --- > src/fw/paravirt.c |

Re: [SeaBIOS] [PATCH v5 1/5] QEMU DMA: Add DMA write capability

ed-off-by: Ben Warren <b...@skyportsystems.com> Reviewed-by: Igor Mammedov <imamm...@redhat.com> > --- > src/fw/paravirt.c | 49 + > src/fw/paravirt.h | 3 +++ > 2 files changed, 52 insertions(+) > > diff --git a/src/fw/paravirt

Re: [SeaBIOS] [PATCH v3 2/2] QEMU fw_cfg: Add command to write back address of file

On Fri, 17 Feb 2017 11:06:54 +0100 Laszlo Ersek wrote: > CC Kevin > > On 02/17/17 07:10, Ben Warren wrote: > > Hi Laszlo > >> On Feb 9, 2017, at 12:24 AM, Laszlo Ersek >> > wrote: > >> > >> On 02/09/17 09:17, Laszlo Ersek

Re: [SeaBIOS] [PATCH 1/2] fw/acpi: Build MADT the way commodity BIOSes do

On Tue, 31 Jan 2017 17:32:55 + "Sironi, Filippo" <sir...@amazon.de> wrote: > > On 30 Jan 2017, at 04:39, Igor Mammedov <imamm...@redhat.com> wrote: > > > > On Fri, 27 Jan 2017 15:57:19 +0100 > > Laszlo Ersek <ler...@redhat.com> wrote:

Re: [SeaBIOS] [PATCH for-1.10-stable] drop "etc/boot-cpus" fw_cfg file and reuse legacy QEMU_CFG_NB_CPUS

On Tue, 15 Nov 2016 11:36:21 +0100 Gerd Hoffmann <kra...@redhat.com> wrote: > On So, 2016-11-13 at 23:05 -0500, Kevin O'Connor wrote: > > On Fri, Nov 11, 2016 at 04:35:15PM +0100, Igor Mammedov wrote: > > > since QEMU_CFG_NB_CPUS not going away anytime soon > >

Re: [SeaBIOS] [PATCH for-1.10-stable] drop "etc/boot-cpus" fw_cfg file and reuse legacy QEMU_CFG_NB_CPUS

On Tue, 15 Nov 2016 09:54:47 -0500 "Kevin O'Connor" <ke...@koconnor.net> wrote: > On Fri, Nov 11, 2016 at 04:35:15PM +0100, Igor Mammedov wrote: > > since QEMU_CFG_NB_CPUS not going away anytime soon > > and serves the same purpose as just added "etc/boot-cp

Re: [SeaBIOS] [PATCH for-1.10-stable] drop "etc/boot-cpus" fw_cfg file and reuse legacy QEMU_CFG_NB_CPUS

On Tue, 15 Nov 2016 11:36:21 +0100 Gerd Hoffmann <kra...@redhat.com> wrote: > On So, 2016-11-13 at 23:05 -0500, Kevin O'Connor wrote: > > On Fri, Nov 11, 2016 at 04:35:15PM +0100, Igor Mammedov wrote: > > > since QEMU_CFG_NB_CPUS not going away anytime soon > >

[SeaBIOS] [PATCH for-1.10-stable] drop "etc/boot-cpus" fw_cfg file and reuse legacy QEMU_CFG_NB_CPUS

PUS instead of it. Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- corresponding QEMU part has been posted to qemu-devel [PATCH for-2.8 0/2] pc: remove redundant fw_cfg file "etc/boot-cpus" --- src/fw/paravirt.h | 1 - src/fw/paravirt.c | 37 ++---

Re: [SeaBIOS] [PATCH v5 0/4] support booting more than 255 CPUs with QEMU

On Tue, 18 Oct 2016 19:13:29 -0400 "Kevin O'Connor" <ke...@koconnor.net> wrote: > On Thu, Oct 13, 2016 at 02:38:24PM +0200, Igor Mammedov wrote: > [...] > > According to SDM, if CPUs have APIC ID more than 254 > > firmware should pass control to OS in x2APIC

[SeaBIOS] [PATCH v5 2/4] smp: consolidate CPU APIC ID detection and accounting

From: Kevin O'Connor <ke...@koconnor.net> Signed-off-by: "Kevin O'Connor" <ke...@koconnor.net> Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- v3: * fix hang on resume path by resetting CountCPUs on every smp_scan v2: * s/count_cpu/apic_id_init/ * call

[SeaBIOS] [PATCH v5 1/4] paravirt: disable legacy bios tables in case of more than 255 CPUs

MPTable doesn't support more than 255 CPUs and QEMU supplies an alternative MADT table which guest will use instead of it. So do not install legacy tables if more than 254 CPUs are provided Signed-off-by: Igor Mammedov <imamm...@redhat.com> Acked-by: Michael S. Tsirkin <m...@redhat.com&

[SeaBIOS] [PATCH v5 0/4] support booting more than 255 CPUs with QEMU

remapping disabled as kernel disables CPUs with APIC ID > 254 and on resume from S3 hangs somewere after getting control from Seabios. Cc: rkrc...@redhat.com Cc: m...@redhat.com Cc: jan.kis...@web.de Cc: kra...@redhat.com Cc: pbonz...@redhat.com Cc: ler...@redhat.com Cc: kra...@redhat.com Igo

[SeaBIOS] [PATCH v5 3/4] add helpers to read etc/boot-cpus at resume time

Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- src/fw/paravirt.h | 3 +++ src/fw/paravirt.c | 38 ++ src/fw/smp.c | 11 ++- 3 files changed, 47 insertions(+), 5 deletions(-) diff --git a/src/fw/paravirt.h b/src/fw/paravirt.h index e

[SeaBIOS] [PATCH v5 4/4] support booting with more than 255 CPUs

6 CPUs use a new rom file "etc/boot-cpus" that QEMU supporting more than 256 CPUs will provide. *1) SDM: Volume 3: EXTENDED XAPIC (X2APIC): Initialization by System Software Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- v4: * use qemu_*_present_cpus_count() hel

Re: [SeaBIOS] [PATCH 5/5] [wip] sercon: initial split-output implementation

On Thu, 13 Oct 2016 09:17:51 +0200 Gerd Hoffmann wrote: > Hi, > > > So far plan is merge it into QEMU 2.8. > > I've amended QEMU counterpart according to Radim's and Paolo's reviews > > and plan to respin it soon. > > No respin yet on the list it seems. What is the

Re: [SeaBIOS] [PATCH 5/5] [wip] sercon: initial split-output implementation

On Tue, 04 Oct 2016 10:49:41 +0200 Gerd Hoffmann wrote: > Hi, > > > Interesting. I'm curious how the memory scan works, because I > > didn't think there was any way to find the vga entry point except > > from the int10 vector. > > Run the init code in emulator? > > >

Re: [SeaBIOS] [PATCH v4 3/5] error out if present cpus count changed during SMP bringup

On Fri, 16 Sep 2016 08:55:49 -0400 "Kevin O'Connor" <ke...@koconnor.net> wrote: > On Fri, Sep 16, 2016 at 01:54:16PM +0200, Igor Mammedov wrote: > > if during SMP bringup a cpu is hotplugged, Seabios might > > silently hung in > > > > while

[SeaBIOS] [PATCH v4 4/5] add helpers to read etc/boot-cpus at resume time

Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- src/fw/paravirt.h | 3 +++ src/fw/paravirt.c | 38 ++ src/fw/smp.c | 11 ++- 3 files changed, 47 insertions(+), 5 deletions(-) diff --git a/src/fw/paravirt.h b/src/fw/paravirt.h index e

[SeaBIOS] [PATCH v4 5/5] support booting with more than 255 CPUs

6 CPUs use a new rom file "etc/boot-cpus" that QEMU supporting more than 256 CPUs will provide. *1) SDM: Volume 3: EXTENDED XAPIC (X2APIC): Initialization by System Software Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- v4: * use qemu_*_present_cpus_count() hel

[SeaBIOS] [PATCH v4 3/5] error out if present cpus count changed during SMP bringup

to make clear what it is counting. Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- src/fw/smp.c | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/src/fw/smp.c b/src/fw/smp.c index 31bcc6a..9040b01 100644 --- a/src/fw/smp.c +++ b/src/fw/smp.c @@

[SeaBIOS] [PATCH v4 1/5] paravirt: disable legacy bios tables in case of more than 255 CPUs

MPTable doesn't support more than 255 CPUs and QEMU supplies an alternative MADT table which guest will use instead of it. So do not install legacy tables if more than 254 CPUs are provided Signed-off-by: Igor Mammedov <imamm...@redhat.com> Acked-by: Michael S. Tsirkin <m...@redhat.com&

[SeaBIOS] [PATCH v4 0/5] support booting more than 255 CPUs with QEMU

next week. Note: S3 wakeup works as expected if linux guest is running with IRQ remapping enabled. However it seems that kernel is buggy with IRQ remapping disabled as kernel disables CPUs with APIC ID > 254 and on resume from S3 hangs somewere after getting control from Seabios. Igor Mamme

[SeaBIOS] [PATCH v4 2/5] smp: consolidate CPU APIC ID detection and accounting

From: Kevin O'Connor <ke...@koconnor.net> Signed-off-by: "Kevin O'Connor" <ke...@koconnor.net> Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- v3: * fix hang on resume path by resetting CountCPUs on every smp_scan v2: * s/count_cpu/apic_id_init/ * call

Re: [SeaBIOS] [PATCH] fix virtio-pci

On Fri, 16 Sep 2016 13:01:46 +0200 Gerd Hoffmann <kra...@redhat.com> wrote: > virtio-pci calls pci_enable_{io,mem}bar with the bar number, > but the functions expect the bar base register offset. > > Reported-by: Igor Mammedov <imamm...@redhat.com> > Signed

Re: [SeaBIOS] guest is unable to boot from virtio drive

On Fri, 16 Sep 2016 11:04:07 +0200 Igor Mammedov <imamm...@redhat.com> wrote: It actually doesn't boot with defconfig either, I'm using current master at 642db1905ab133007d7427b6758a2103fb09a19a > This happens only when combination of build options > CONFIG_RELOCATE_INIT=n + CONFIG

[SeaBIOS] guest is unable to boot from virtio drive

This happens only when combination of build options CONFIG_RELOCATE_INIT=n + CONFIG_DEBUG_LEVEL=3 to reproduce compile seabios defconfig + above options and start guest with a single virtio drive: -drive if=virtio,file=guest.img As result one gets: No bootable device. here is debug log:

Re: [SeaBIOS] [PATCH v3 3/3] support booting with more than 255 CPUs

On Wed, 10 Aug 2016 11:25:41 -0400 "Kevin O'Connor" <ke...@koconnor.net> wrote: > On Wed, Aug 10, 2016 at 12:59:16PM +0200, Igor Mammedov wrote: > > On Mon, 8 Aug 2016 18:42:07 -0400 > > "Kevin O'Connor" <ke...@koconnor.net> wrote: > > >

Re: [SeaBIOS] [PATCH v3 3/3] support booting with more than 255 CPUs

On Mon, 8 Aug 2016 18:42:07 -0400 "Kevin O'Connor" <ke...@koconnor.net> wrote: > On Fri, Aug 05, 2016 at 12:47:29PM +0200, Igor Mammedov wrote: > > SDM[*1] says that if there are CPUs with APIC ID > > greater than 254, BIOS is to pass control to OS > > i

Re: [SeaBIOS] [PATCH v3 2/3] smp: refactor present CPU APIC ID detection and counting

On Mon, 8 Aug 2016 18:37:13 -0400 "Kevin O'Connor" <ke...@koconnor.net> wrote: > On Fri, Aug 05, 2016 at 12:47:28PM +0200, Igor Mammedov wrote: > > From: Kevin O'Connor <ke...@koconnor.net> > > > > Signed-off-by: "Kevin O'Connor" <ke.

[SeaBIOS] [PATCH v3 1/3] paravirt: disable legacy bios tables in case of more than 255 CPUs

MPTable doesn't support more than 255 CPUs and QEMU supplies an alternative MADT table which guest will use instead of it. So do not install legacy tables if more than 254 CPUs are provided Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- src/fw/paravirt.c | 6 -- 1 file chan

[SeaBIOS] [PATCH v3 3/3] support booting with more than 255 CPUs

6 CPUs use a new rom file "etc/boot-cpus" that QEMU supporting more than 256 CPUs will provide. *1) SDM: Volume 3: EXTENDED XAPIC (X2APIC): Initialization by System Software Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- v2: * merge handle_x2apic() into apic_id_ini

[SeaBIOS] [PATCH v3 2/3] smp: refactor present CPU APIC ID detection and counting

From: Kevin O'Connor <ke...@koconnor.net> Signed-off-by: "Kevin O'Connor" <ke...@koconnor.net> Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- v2: * s/count_cpu/apic_id_init/ * call apic_id_init() after sending SIPI, it will be needed for switching BSP

[SeaBIOS] [PATCH v3 0/3] support booting more than 255 CPUs with QEMU

for the next merge window: https://www.mail-archive.com/qemu-devel@nongnu.org/msg390671.html Igor Mammedov (2): paravirt: disable legacy bios tables in case of more than 255 CPUs support booting with more than 255 CPUs Kevin O'Connor (1): smp: refactor present CPU APIC ID detection

Re: [SeaBIOS] [PATCH v2 0/4] support booting more than 255 CPUs with QEMU

On Mon, 20 Jun 2016 13:51:28 +0200 Gerd Hoffmann wrote: > Hi, > > > I need to dust RFC off and respin as Paolo wanted to sync APIC ID > > other way than in RFC and also on list there is v2 ACPI refactoring > > that x2APIC enablement depends on. > > Soft freeze is only one

Re: [SeaBIOS] [PATCH v2 0/4] support booting more than 255 CPUs with QEMU

On Mon, 20 Jun 2016 10:45:37 +0200 Gerd Hoffmann <kra...@redhat.com> wrote: > On Mo, 2016-05-16 at 21:00 -0400, Kevin O'Connor wrote: > > On Wed, May 11, 2016 at 12:03:37PM +0200, Igor Mammedov wrote: > > > Changelog since: > > > v1: > > > * s

Re: [SeaBIOS] [PATCH 4/4] cleanup smp_setup()

On Wed, 11 May 2016 10:08:11 -0400 "Kevin O'Connor" <ke...@koconnor.net> wrote: > On Wed, May 11, 2016 at 11:50:36AM +0200, Igor Mammedov wrote: > > On Tue, 10 May 2016 16:43:34 +0200 > > Igor Mammedov <imamm...@redhat.com> wrote: > > > >

Re: [SeaBIOS] [Qemu-devel] [RFC PATCH v4] fw/pci: Add support for mapping Intel IGD via QEMU

On Tue, 10 May 2016 09:19:52 -0600 Alex Williamson wrote: > On Tue, 23 Feb 2016 10:22:33 -0500 > "Kevin O'Connor" wrote: > > > On Tue, Feb 16, 2016 at 02:39:27PM -0700, Alex Williamson wrote: > > > QEMU provides two fw_cfg files to support IGD.

[SeaBIOS] [PATCH v2 4/4] cleanup smp_setup()

MaxCountCPUs could never be 0 or less CountCPUs anymore, remove code that wouldn't be executed. Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- src/fw/smp.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/fw/smp.c b/src/fw/smp.c index dfb8425..cb40ec6 100644 --- a/src/fw

[SeaBIOS] [PATCH v2 2/4] smp: refactor present CPU APIC ID detection and counting

From: Kevin O'Connor <ke...@koconnor.net> Signed-off-by: "Kevin O'Connor" <ke...@koconnor.net> Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- v2: * s/count_cpu/apic_id_init/ * call apic_id_init() after sending SIPI, it will be needed for switching BSP

[SeaBIOS] [PATCH v2 3/4] support booting with more than 255 CPUs

6 CPUs use a new rom file "etc/boot-cpus" that QEMU supporting more than 256 CPUs will provide. *1) SDM: Volume 3: EXTENDED XAPIC (X2APIC): Initialization by System Software Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- v2: * merge handle_x2apic() into a

[SeaBIOS] [PATCH v2 1/4] paravirt: disable legacy bios tables in case of more than 255 CPUs

MPTable doesn't support more than 255 CPUs and QEMU supplies an alternative MADT table which guest will use instead of it. So do not install legacy tables if more than 254 CPUs are provided Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- src/fw/paravirt.c | 6 -- 1 file chan

[SeaBIOS] [PATCH v2 0/4] support booting more than 255 CPUs with QEMU

Igor Mammedov (3): paravirt: disable legacy bios tables in case of more than 255 CPUs support booting with more than 255 CPUs cleanup smp_setup() Kevin O'Connor (1): smp: refactor present CPU APIC ID detection and counting src/fw/paravirt.c | 6 -- src/fw/smp.c | 57

Re: [SeaBIOS] [PATCH 0/4] support booting more than 255 CPUs with QEMU

On Tue, 10 May 2016 16:43:30 +0200 Igor Mammedov <imamm...@redhat.com> wrote: Probably question to Kevin, I've tried to make AP bootstrap run in parallel to speed up smp_setup with many CPUs. However it hangs and I couldn't debug it. Debugging works fine in 16bit mode as described i

Re: [SeaBIOS] [PATCH 4/4] cleanup smp_setup()

On Tue, 10 May 2016 16:43:34 +0200 Igor Mammedov <imamm...@redhat.com> wrote: > MaxCountCPUs could never be 0 or less CountCPUs > anymore, remove code that wouldn't be executed. > > Signed-off-by: Igor Mammedov <imamm...@redhat.com> > --- > src/fw/smp.c | 2 --

Re: [SeaBIOS] [PATCH 3/4] support booting with more than 255 CPUs

On Tue, 10 May 2016 11:20:54 -0400 "Kevin O'Connor" <ke...@koconnor.net> wrote: > On Tue, May 10, 2016 at 04:43:33PM +0200, Igor Mammedov wrote: > > SDM[*1] says that if there are CPUs with APIC ID > > greater than 254, BIOS is to pass control to OS > > i

[SeaBIOS] [PATCH 2/4] smp: refactor present CPU APIC ID detection and counting

From: Kevin O'Connor <ke...@koconnor.net> Signed-off-by: "Kevin O'Connor" <ke...@koconnor.net> Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- src/fw/smp.c | 31 ++- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a

[SeaBIOS] [PATCH 0/4] support booting more than 255 CPUs with QEMU

more than 254 firmware should pass control to OS in x2APIC mode. This series adds x2APIC bootstrap initialization. QEMU side of x2APIC support: https://lists.gnu.org/archive/html/qemu-devel/2016-05/msg01094.html Igor Mammedov (3): paravirt: disable legacy bios tables in case of more than 255 CPUs

[SeaBIOS] [PATCH 1/4] paravirt: disable legacy bios tables in case of more than 255 CPUs

MPTable doesn't support more than 255 CPUs and QEMU supplies an alternative MADT table which guest will use instead of it. So do not install legacy tables if more than 254 CPUs are provided Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- src/fw/paravirt.c | 6 -- 1 file chan

Re: [SeaBIOS] [PATCH RFC 2/2] support booting with more than 255 CPUs

On Mon, 9 May 2016 11:49:36 -0400 "Kevin O'Connor" <ke...@koconnor.net> wrote: > On Mon, May 09, 2016 at 11:43:54AM +0200, Igor Mammedov wrote: > > SDM[*1] says that if there are CPUs with APIC ID > > greater than 254, BIOS is to pass control to OS > > i

Re: [SeaBIOS] [PATCH RFC 1/2] paravirt: disable MPTable in case of more than 255 CPUs

On Mon, 9 May 2016 11:12:25 -0400 "Kevin O'Connor" <ke...@koconnor.net> wrote: > On Mon, May 09, 2016 at 11:43:53AM +0200, Igor Mammedov wrote: > > MPTable doesn't support more than 254 CPUs and > > QEMU supplies an alternative MADT table which > > guest will

[SeaBIOS] [PATCH RFC 1/2] paravirt: disable MPTable in case of more than 255 CPUs

MPTable doesn't support more than 254 CPUs and QEMU supplies an alternative MADT table which guest will use instead of it. So do not install MPTable if more than 254 CPUs are provided. Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- src/fw/mptable.c | 4 1 file changed, 4 inse

[SeaBIOS] [PATCH RFC 0/2] support booting more than 255 CPUs with QEMU

According to SDM, if CPUs have APIC ID more than 254 firmware should pass control to OS in x2APIC mode. This series adds x2APIC bootstrap initialization. QEMU side of x2APIC support: https://lists.gnu.org/archive/html/qemu-devel/2016-05/msg01094.html Igor Mammedov (2): paravirt: disable

[SeaBIOS] [PATCH RFC 2/2] support booting with more than 255 CPUs

6 CPUs use a new rom file "etc/boot-cpus" that QEMU supporting more than 256 CPUs will provide. *1) SDM: Volume 3: EXTENDED XAPIC (X2APIC): Initialization by System Software Signed-off-by: Igor Mammedov <imamm...@redhat.com> --- src/fw/smp.c | 48 +++

Re: [SeaBIOS] [Qemu-devel] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Sat, 13 Feb 2016 18:03:31 -0700 Alex Williamson wrote: > On Sat, 13 Feb 2016 19:20:32 -0500 > "Kevin O'Connor" wrote: > > > On Sat, Feb 13, 2016 at 01:57:09PM -0700, Alex Williamson wrote: > > > On Sat, 13 Feb 2016 15:05:09 -0500 > > >

Re: [SeaBIOS] [RFC PATCH v2] fw/pci: Add support for mapping Intel IGD OpRegion via QEMU

On Tue, 02 Feb 2016 13:10:37 -0700 Alex Williamson wrote: > When assigning Intel IGD graphics via QEMU/vfio, the OpRegion for the > device may be exposed as a fw_cfg file. Allocate space for this, copy > the contents and write the ASL Storage register (0xFC) to point

Re: [SeaBIOS] [PATCH v5 2/3] target-i386: reserve RCRB mmio space in ACPI DSDT table

On Mon, 22 Jun 2015 20:10:28 -0300 Paulo Alcantara pca...@gmail.com wrote: Also I've stumbled upon http://download.intel.com/design/chipsets/applnots/29227301.pdf don't we need to implement WDDT ACPI table as well? This block is mapped into memory space, using the Root Complex Base Address

Re: [SeaBIOS] [PATCH v4 2/3] target-i386: reserve RCRB mmio space in ACPI DSDT table

On Tue, 23 Jun 2015 12:58:13 +0200 Michael S. Tsirkin m...@redhat.com wrote: On Tue, Jun 23, 2015 at 12:38:59PM +0200, Igor Mammedov wrote: On Sun, 21 Jun 2015 21:37:02 -0300 Paulo Alcantara pca...@gmail.com wrote: This block is mapped into memory space, using the Root Complex Base

Re: [SeaBIOS] [PATCH v5 2/3] target-i386: reserve RCRB mmio space in ACPI DSDT table

On Mon, 22 Jun 2015 20:10:28 -0300 Paulo Alcantara pca...@gmail.com wrote: This block is mapped into memory space, using the Root Complex Base Address (RCBA) register of the PCI-to-LPC bridge. Accesses in this space must be limited to 32-(DW) bit quantities. Burst accesses are not allowed.

Re: [SeaBIOS] [PATCH v4 2/3] target-i386: reserve RCRB mmio space in ACPI DSDT table

On Sun, 21 Jun 2015 21:37:02 -0300 Paulo Alcantara pca...@gmail.com wrote: This block is mapped into memory space, using the Root Complex Base Address (RCBA) register of the PCI-to-LPC bridge. Accesses in this space must be limited to 32-(DW) bit quantities. Burst accesses are not allowed.

Re: [SeaBIOS] [PATCH 2/3] Support for TPM Physical Presence Interface

On Fri, 8 May 2015 13:45:47 -0400 Stefan Berger stef...@linux.vnet.ibm.com wrote: This patch implements the specification found here: http://www.trustedcomputinggroup.org/resources/tcg_physical_presence_interface_specification It adds the necessary BIOS code so that for example an

Re: [SeaBIOS] [Qemu-devel] [PATCH v4 for-2.3 01/25] acpi: fix aml_equal term implementation

On Mon, 9 Mar 2015 12:04:51 +0100 Michael S. Tsirkin m...@redhat.com wrote: On Mon, Mar 09, 2015 at 11:28:22AM +0100, Igor Mammedov wrote: On Sun, 8 Mar 2015 13:16:03 +0200 Marcel Apfelbaum mar...@redhat.com wrote: The DefLEqual op does not have a target operand. Remove

Re: [SeaBIOS] [Qemu-devel] [PATCH v4 for-2.3 05/25] acpi: add aml_index() term

On Sun, 8 Mar 2015 13:16:07 +0200 Marcel Apfelbaum mar...@redhat.com wrote: Add encoding for ACPI DefIndex Opcode. Signed-off-by: Marcel Apfelbaum mar...@redhat.com --- hw/acpi/aml-build.c | 13 + include/hw/acpi/aml-build.h | 1 + 2 files changed, 14 insertions(+)

Re: [SeaBIOS] [Qemu-devel] [PATCH v4 for-2.3 01/25] acpi: fix aml_equal term implementation

On Sun, 8 Mar 2015 13:16:03 +0200 Marcel Apfelbaum mar...@redhat.com wrote: The DefLEqual op does not have a target operand. Remove it. Signed-off-by: Marcel Apfelbaum mar...@redhat.com Reviewed-by: Igor Mammedov imamm...@redhat.com --- hw/acpi/aml-build.c | 1 - 1 file changed, 1

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 for-2.3 02/24] acpi: add aml_add() term

On Thu, 5 Mar 2015 16:55:00 +0200 Marcel Apfelbaum mar...@redhat.com wrote: Add encoding for ACPI DefAdd Opcode. Signed-off-by: Marcel Apfelbaum mar...@redhat.com Reviewed-by: Igor Mammedov imamm...@redhat.com --- hw/acpi/aml-build.c | 10 ++ include/hw/acpi/aml-build.h

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 for-2.3 01/24] acpi: add aml_or() term

On Thu, 5 Mar 2015 16:54:59 +0200 Marcel Apfelbaum mar...@redhat.com wrote: Add encoding for ACPI DefOr Opcode. Signed-off-by: Marcel Apfelbaum mar...@redhat.com Reviewed-by: Igor Mammedov imamm...@redhat.com --- hw/acpi/aml-build.c | 10 ++ include/hw/acpi/aml-build.h

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 for-2.3 03/24] acpi: add aml_lless() term

On Thu, 5 Mar 2015 16:55:01 +0200 Marcel Apfelbaum mar...@redhat.com wrote: Add encoding for ACPI DefLLess Opcode. Signed-off-by: Marcel Apfelbaum mar...@redhat.com Reviewed-by: Igor Mammedov imamm...@redhat.com --- hw/acpi/aml-build.c | 9 + include/hw/acpi/aml-build.h

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 for-2.3 08/24] acpi: add aml_while() term

On Thu, 5 Mar 2015 16:55:06 +0200 Marcel Apfelbaum mar...@redhat.com wrote: Add encoding for ACPI DefWhile Opcode. Signed-off-by: Marcel Apfelbaum mar...@redhat.com Reviewed-by: Igor Mammedov imamm...@redhat.com --- hw/acpi/aml-build.c | 8 include/hw/acpi/aml-build.h

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 for-2.3 04/24] acpi: add aml_index() term

On Thu, 5 Mar 2015 16:55:02 +0200 Marcel Apfelbaum mar...@redhat.com wrote: Add encoding for ACPI DefIndex Opcode. Signed-off-by: Marcel Apfelbaum mar...@redhat.com --- hw/acpi/aml-build.c | 10 ++ include/hw/acpi/aml-build.h | 1 + 2 files changed, 11 insertions(+)

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 for-2.3 05/24] acpi: add aml_shiftleft() term

On Thu, 5 Mar 2015 16:55:03 +0200 Marcel Apfelbaum mar...@redhat.com wrote: Add encoding for ACPI DefShiftLeft Opcode. Signed-off-by: Marcel Apfelbaum mar...@redhat.com Reviewed-by: Igor Mammedov imamm...@redhat.com --- hw/acpi/aml-build.c | 10 ++ include/hw/acpi/aml

Re: [SeaBIOS] [Qemu-devel] [PATCH v3 for-2.3 06/24] acpi: add aml_shiftright() term

On Thu, 5 Mar 2015 16:55:04 +0200 Marcel Apfelbaum mar...@redhat.com wrote: Add encoding for ACPI DefShiftRight Opcode. Signed-off-by: Marcel Apfelbaum mar...@redhat.com Reviewed-by: Igor Mammedov imamm...@redhat.com --- hw/acpi/aml-build.c | 10 ++ include/hw/acpi/aml

Re: [SeaBIOS] [Qemu-devel] [PATCH RFC V2 04/17] hw/acpi: add _CRS method for extra root busses

On Mon, 16 Feb 2015 11:54:04 +0200 Marcel Apfelbaum mar...@redhat.com wrote: Save the IO/mem/bus numbers ranges assigned to the extra root busses to be removed from the root bus 0 range. Is it possible to make BIOS program extra buses and root bus 0 in sane way so their resources won't

Re: [SeaBIOS] [PATCH 3/3] Allow using full io region on q35.

On Tue, 20 May 2014 12:20:37 +0200 Gerd Hoffmann kra...@redhat.com wrote: If qemu is new enough to support acpi table loading, then go move pmbase out of the way. This allows to use the whole 0x1000 - 0x io address space on q35. piix has hotplug ports in the 0xa000 - 0xafff area, so we

Re: [SeaBIOS] [PATCH v3] i386: Add _PXM ACPI method to CPU objects

, 0x5f, -0x68 -}; -static unsigned char ssdt_proc_id[] = { -0x38 -}; -static unsigned char ssdt_proc_end[] = { -0x78 +0x68, +0x14, +0xb, +0x5f, +0x50, +0x58, +0x4d, +0x0, +0xa4, +0x43, +0x50, +0x58, +0x4d }; static unsigned char ssdt_proc_start[] = { 0x24 Reviewed-By: Igor

Re: [SeaBIOS] [PATCH 6/6] pci: map 64-bit BARs at location provided by emulator

. Based-on-patch-by: Igor Mammedov imamm...@redhat.com Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/fw/pciinit.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 3de0c7e..654697d 100644 --- a/src/fw/pciinit.c +++ b

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