Re: [SeaBIOS] GeodeVGA is not initialized during SeaBIOS execution

On Mon, Jul 11, 2016 at 02:23:12AM +0300, Andrey Korolyov wrote: > Hi, > > as per Kevin`s suggestion, I am posting initialization log (mixed one) > from initialization of the GeodeLX board. As it could be clearly seen > from the log, VGA option ROM was never called and executed during the >

Re: [SeaBIOS] [PATCH] restore MSRs on S3 resume

te_msrs on the BSP followed by smp_scan to initialize the APs. Reported-by: Laszlo Ersek <ler...@redhat.com> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Kevin O'Connor <ke...@koconnor.net> diff --git a/src/fw/smp.c b/src/fw/smp.c index 6e706e4..719d

Re: [SeaBIOS] [PATCH 1/3] vgabios: Remove special case of dh==0xff in handle_1013()

On Mon, Jul 04, 2016 at 12:41:14PM -0400, Kevin O'Connor wrote: > The original "lgpl vgabios" had a special case for dh==0xff in its > int1013 (write string) code. There does not appear to be any VGABIOS > documentation supporting this as an externally available fea

Re: [SeaBIOS] [PATCH 3/3] add serial console support

On Tue, Jul 05, 2016 at 05:07:08PM +0200, Gerd Hoffmann wrote: > I also hacked up a patch to send output to both vga + serial: > > https://www.kraxel.org/cgit/seabios/commit/?h=serial=3afd7b8bb96126b00989f3ae09f451bbec4f00f7 > > Not working stable though, seems to corrupt memory, not sure why. >

Re: [SeaBIOS] Issues building SeaBIOS with gcc > 4.8

On Tue, Jul 05, 2016 at 03:49:34PM +0200, Roger Pau Monné wrote: > Hello, > > I'm seeing the following issue when building SeaBIOS with gcc > 4.8: > > Compiling whole program out/ccode32flat.o > Compiling whole program out/code32seg.o > Compiling whole program out/ccode16.o >

Re: [SeaBIOS] [PATCH 3/3] add serial console support

On Mon, Jul 04, 2016 at 10:39:54PM +0200, Gerd Hoffmann wrote: > Signed-off-by: Gerd Hoffmann Not sure if this is still an RFC. I think it needs to have a Kconfig option. It should probably also have runtime enable option. [...] > --- a/Makefile > +++ b/Makefile > @@ -29,7

Re: [SeaBIOS] [PATCH 1/3] std: add cp437 to unicode map

On Mon, Jul 04, 2016 at 10:39:52PM +0200, Gerd Hoffmann wrote: > Signed-off-by: Gerd Hoffmann Nice! [...] > --- /dev/null > +++ b/src/std/cp437.h Instead of making a header file and including it in an array in the C code I think it would be better to instead introduce

Re: [SeaBIOS] [RFC PATCH 1/2] serial console, output

On Mon, Jul 04, 2016 at 06:03:30PM +0200, Paolo Bonzini wrote: > On 04/07/2016 18:00, Kevin O'Connor wrote: > > Does anyone know where one can find the original svn commit history > > for sgabios? Seems the original google code repo is no longer > > present. > > There

[SeaBIOS] [PATCH 3/3] vgabios: Simplify set_cursor_pos()

Rework set_cursor_pos() to be slightly simpler. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- vgasrc/vgabios.c | 28 ++-- 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/vgasrc/vgabios.c b/vgasrc/vgabios.c index 2593e03..cfb6ba2

Re: [SeaBIOS] [RFC PATCH 1/2] serial console, output

On Mon, Jul 04, 2016 at 11:26:48AM -0400, Kevin O'Connor wrote: > At one point I looked through the sgabios code and was able to > understand how it did caching. I'll take another look and see if I > can describe it. So, if I read the sgabios code correctly, it allocates a buffer of

Re: [SeaBIOS] [RFC PATCH 2/2] serial console, input

On Mon, Jul 04, 2016 at 11:16:45AM +0200, Gerd Hoffmann wrote: > Hi, > > > > +#define FLAG_CTRL (1<<0) > > > +#define FLAG_SHIFT (1<<1) > > > + > > > +VARLOW struct { > > > +u8 flags; > > > +u8 scancode; > > > +} termchr[256] = { > > > +[ '1'] = { .scancode = 0x02,

Re: [SeaBIOS] [RFC PATCH 2/2] serial console, input

On Fri, Jul 01, 2016 at 01:07:39PM -0400, Kevin O'Connor wrote: > If I understand correctly, most keys are sent on the serial port as > single bytes, but there are a few keys that are sent as multi-byte > sequences. There's a lot of complexity to implement buffering for > that unus

Re: [SeaBIOS] [RFC PATCH 2/2] serial console, input

On Fri, Jul 01, 2016 at 12:54:31PM +0200, Gerd Hoffmann wrote: > Signed-off-by: Gerd Hoffmann > --- > src/clock.c | 1 + > src/serial.c | 255 > +++ > src/util.h | 1 + > 3 files changed, 257 insertions(+) > >

Re: [SeaBIOS] [RFC PATCH 1/2] serial console, output

On Fri, Jul 01, 2016 at 12:54:30PM +0200, Gerd Hoffmann wrote: > Signed-off-by: Gerd Hoffmann Thanks. See my comments below. [...] > --- a/src/misc.c > +++ b/src/misc.c > @@ -11,6 +11,7 @@ > #include "output.h" // debug_enter > #include "stacks.h" // call16_int > #include

Re: [SeaBIOS] [PATCH v2 0/4] support booting more than 255 CPUs with QEMU

On Fri, Jun 24, 2016 at 10:12:12AM +0200, Paolo Bonzini wrote: > On 24/06/2016 10:06, Gerd Hoffmann wrote: > >>> If there are any other suggestions for cherry-picks please speak up now. > >> > >> I would like to have "[PATCH v3] fw/msr_feature_control: add support to > >> set

Re: [SeaBIOS] [PATCH 0/2] virtio: pci cfg access

On Fri, Jun 17, 2016 at 01:09:05PM +0200, Gerd Hoffmann wrote: > Hi, > > I'm sure I had sent this before, but appearently totally forgot about > it. Just tested booting with virtio bars mapped above 4G, didn't work. > Investigated, found this bitroting in a local branch. Undusted it, >

Re: [SeaBIOS] UEFI project ideas

On Mon, Jun 06, 2016 at 10:05:31PM +0200, Rudolf Marek wrote: > Hi all, > > I noticed that seabios/libpayload could have interresting use cases and I want > to share/discuss them. > > 1) Have a SeaBIOS be a UEFI application. This would benefit on UEFI platforms > without CSM. That would be

Re: [SeaBIOS] [PATCH]:splash: Skip the RGB555 mode

On Fri, May 20, 2016 at 03:26:32PM +, Zheng Bao wrote: > Current JPEG decoding uses the RGB888 or RGB565. So we need to skip > RGB555 mode. Thanks. I updated the indentation and committed this patch. -Kevin ___ SeaBIOS mailing list

Re: [SeaBIOS] [PATCH] keyboard: Inject serial port input as keypresses

On Fri, May 20, 2016 at 02:31:09PM +0300, Kyösti Mälkki wrote: > Maps characters received from serial port as INT16h keypresses. > This enables making choice of boot media over serial port. > > Source extracted from SageBIOS release for PC Engines apu1. > af6c8ab3b85d1a5a9fbeb41efa30a1ef

Re: [SeaBIOS] [PATCH 1/2] scripts/acpi_*: use env python instead of python in shebang

On Thu, May 19, 2016 at 02:25:19AM +0200, Alexander Couzens wrote: > python should be called via env to support virtualenvs Is this a general cleanup, or did you run into a specific problem? These scripts are typically run from the makefile which runs them with the interpreter specified:

Re: [SeaBIOS] [PATCH 2/2] use python2 instead of python

On Thu, May 19, 2016 at 02:25:20AM +0200, Alexander Couzens wrote: > python is ambiguous. it could mean python2 or python3. The scripts were written to run with either python2 or python3. Did you run into a compatibility issue? -Kevin ___ SeaBIOS

Re: [SeaBIOS] [PATCH v2 0/4] support booting more than 255 CPUs with QEMU

On Wed, May 11, 2016 at 12:03:37PM +0200, Igor Mammedov wrote: > Changelog since: > v1: > * s/count_cpu/apic_id_init/ > * merge handle_x2apic() into apic_id_init() > RFC: > * move out max-cpus check out of mptable_setup() > * factor out CPU counting/apic ID detection in

Re: [SeaBIOS] [PATCH] tcgbios: Remove unused const variable

On Fri, May 13, 2016 at 07:29:30AM +0200, Paul Menzel wrote: > Date: Fri, 13 May 2016 07:10:32 +0200 > Subject: [PATCH 2/2] tcgbios: Remove unused const variable > > Remove the unused array `PhysicalPresence_CMD_DISABLE` to fix the GCC 6 > warnings below. Thanks. Your patches got corrupted, but

Re: [SeaBIOS] [RFC PATCH v4] fw/pci: Add support for mapping Intel IGD via QEMU

On Tue, May 10, 2016 at 09:19:52AM -0600, Alex Williamson wrote: > On Tue, 23 Feb 2016 10:22:33 -0500 > "Kevin O'Connor" <ke...@koconnor.net> wrote: > > > On Tue, Feb 16, 2016 at 02:39:27PM -0700, Alex Williamson wrote: > > > QEMU provides two fw_cf

Re: [SeaBIOS] [PATCH 0/4] support booting more than 255 CPUs with QEMU

On Wed, May 11, 2016 at 12:02:40PM +0200, Igor Mammedov wrote: > On Tue, 10 May 2016 16:43:30 +0200 > Igor Mammedov wrote: > > Probably question to Kevin, > I've tried to make AP bootstrap run in parallel > to speed up smp_setup with many CPUs. > However it hangs and I

Re: [SeaBIOS] [PATCH 4/4] cleanup smp_setup()

On Wed, May 11, 2016 at 11:50:36AM +0200, Igor Mammedov wrote: > On Tue, 10 May 2016 16:43:34 +0200 > Igor Mammedov wrote: > > > MaxCountCPUs could never be 0 or less CountCPUs > > anymore, remove code that wouldn't be executed. > > > > Signed-off-by: Igor Mammedov

Re: [SeaBIOS] [PATCH 3/4] support booting with more than 255 CPUs

On Tue, May 10, 2016 at 05:31:33PM +0200, Igor Mammedov wrote: > On Tue, 10 May 2016 11:20:54 -0400 > "Kevin O'Connor" <ke...@koconnor.net> wrote: > > > On Tue, May 10, 2016 at 04:43:33PM +0200, Igor Mammedov wrote: > > > SDM[*1] says that if there are

Re: [SeaBIOS] [PATCH RFC 1/2] paravirt: disable MPTable in case of more than 255 CPUs

On Tue, May 10, 2016 at 02:13:35PM +0200, Igor Mammedov wrote: > On Mon, 9 May 2016 11:12:25 -0400 > "Kevin O'Connor" <ke...@koconnor.net> wrote: > > > On Mon, May 09, 2016 at 11:43:53AM +0200, Igor Mammedov wrote: > > > MPTable doesn't support mo

Re: [SeaBIOS] [PATCH RFC 2/2] support booting with more than 255 CPUs

On Mon, May 09, 2016 at 11:43:54AM +0200, Igor Mammedov wrote: > SDM[*1] says that if there are CPUs with APIC ID > greater than 254, BIOS is to pass control to OS > in x2APIC mode. Use the fact that QEMU passes in > "etc/max-cpus" max possible "APIC ID + 1" to > detect need for x2APIC mode. Also

Re: [SeaBIOS] [PATCH RFC 1/2] paravirt: disable MPTable in case of more than 255 CPUs

On Mon, May 09, 2016 at 11:43:53AM +0200, Igor Mammedov wrote: > MPTable doesn't support more than 254 CPUs and > QEMU supplies an alternative MADT table which > guest will use instead of it. So do not install > MPTable if more than 254 CPUs are provided. > > Signed-off-by: Igor Mammedov

Re: [SeaBIOS] qemu-kvm: SeaBIOS 1.9.0 and above cannot boot Windows 10 from harddisk

On Tue, Apr 26, 2016 at 11:16:20PM +0200, Johannes Krottmayer wrote: > Am 2016-04-26 um 22:38 schrieb Kevin O'Connor: > [...] > > To report a SeaBIOS issue, the SeaBIOS log is needed. Please see > > http://www.seabios.org/Debugging#Diagnostic_information > > $ qemu-syst

Re: [SeaBIOS] qemu-kvm: SeaBIOS 1.9.0 and above cannot boot Windows 10 from harddisk

On Tue, Apr 26, 2016 at 10:10:04PM +0200, Johannes Krottmayer wrote: > I have following problem... To report a SeaBIOS issue, the SeaBIOS log is needed. Please see http://www.seabios.org/Debugging#Diagnostic_information [...] > QEMU output with SeaBIOS 1.9.0 and above: Did it work with some

Re: [SeaBIOS] [PATCH 2/2] shadow: Batch PCI config writes

On Tue, Apr 05, 2016 at 12:51:56PM -0400, Kevin O'Connor wrote: > Enabling and disabling shadow ram on QEMU is slow. Batch the PCI > writes to reduce the number of memory changes QEMU must implement. FYI, I committed this change. -Kevin ___ S

Re: [SeaBIOS] [PATCH 2/2] scsi: Launch a thread when scanning for drives in the scsi drivers

On Tue, Apr 05, 2016 at 01:06:32PM -0400, Kevin O'Connor wrote: > Signed-off-by: Kevin O'Connor <ke...@koconnor.net> FYI, I committed this change. -Kevin ___ SeaBIOS mailing list SeaBIOS@seabios.org https://www.coreboot.org/mailman/listinfo/seabios

Re: [SeaBIOS] [PATCH 2/2] disk: Avoid stack_hop() path if already on the extra stack

On Thu, Mar 31, 2016 at 02:50:32PM -0400, Kevin O'Connor wrote: > If CONFIG_ENTRY_EXTRASTACK is set (enabled by default) then the 16bit > disk interface code is already running on the extra stack and it is > not necessary to support stack switching on each disk request. FYI, I

Re: [SeaBIOS] Add support for legacy USB keyboard/mouse (PS/2 emulation for USB?)

On Sat, Apr 16, 2016 at 01:26:43AM +0200, Adam Rutkowski wrote: > Hello, > > I think this is the right place to write about this. From a few days > I'm fighting with not USB-aware OS-es in QEMU (like Windows 98, IBM > OS/2, MS-DOS etc.). When I assign real USB keyboard and mouse to VM, > keyboard

Re: [SeaBIOS] [RFC] Document and rework debug levels

On Wed, Apr 06, 2016 at 07:58:28PM +0200, Laszlo Ersek wrote: > On 04/06/16 19:52, Kevin O'Connor wrote: > > On Wed, Apr 06, 2016 at 07:38:49PM +0200, Laszlo Ersek wrote: > >> On 04/06/16 19:07, Kevin O'Connor wrote: > >>> There are a number of debug le

Re: [SeaBIOS] [RFC] Document and rework debug levels

On Wed, Apr 06, 2016 at 07:38:49PM +0200, Laszlo Ersek wrote: > On 04/06/16 19:07, Kevin O'Connor wrote: > > There are a number of debug levels in the SeaBIOS code today. > > Unfortunately, much of the code does not follow any particular > > standard for whi

[SeaBIOS] [RFC] Document and rework debug levels

There are a number of debug levels in the SeaBIOS code today. Unfortunately, much of the code does not follow any particular standard for which debug level to use. This is becoming cumbersome for a few reasons: - some people want fewer debug messages to reduce boot time, but still want

[SeaBIOS] [PATCH 1/2] virtio: Use threads when scanning for virtio devices

Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/virtio-blk.c | 6 -- src/hw/virtio-scsi.c | 6 -- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/hw/virtio-blk.c b/src/hw/virtio-blk.c index 2dfd0c3..dca7855 100644 --- a/src/hw/virtio-blk.c +++ b/

[SeaBIOS] [PATCH 2/2] scsi: Launch a thread when scanning for drives in the scsi drivers

Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/esp-scsi.c | 8 src/hw/lsi-scsi.c | 8 src/hw/megasas.c | 7 +++ src/hw/mpt-scsi.c | 23 ++- src/hw/pvscsi.c | 8 5 files changed, 25 insertions(+), 29 deletions(-) diff

[SeaBIOS] [PATCH 2/2] shadow: Batch PCI config writes

Enabling and disabling shadow ram on QEMU is slow. Batch the PCI writes to reduce the number of memory changes QEMU must implement. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/fw/shadow.c | 55 ++- 1 file changed, 38 inse

[SeaBIOS] [PATCH 1/2] optionroms: Drop support for CONFIG_OPTIONROMS_DEPLOYED

No modern software uses this option and it complicates the code. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/Kconfig | 8 src/fw/shadow.c | 15 +- src/optionroms.c | 61 3 files chang

Re: [SeaBIOS] virtio-blk ... block size 4096 is unsupported

On Tue, Apr 05, 2016 at 02:31:53PM +0200, Laszlo Ersek wrote: > On 04/05/16 06:25, James Shimer wrote: > > I've been doing some testing if KVM with 4K physical sector virtio > > disks and they work with KVM as a none boot disk. We'd like to be > > able to boot a 4k physical sector disk in KVM, is

[SeaBIOS] [PATCH 2/2] disk: Avoid stack_hop() path if already on the extra stack

If CONFIG_ENTRY_EXTRASTACK is set (enabled by default) then the 16bit disk interface code is already running on the extra stack and it is not necessary to support stack switching on each disk request. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/block.c | 4 src/disk.c

[SeaBIOS] [PATCH 1/2] block: Move send_disk_op() from block.c to disk.c

The send_disk_op() function is only called from the 16bit handlers found in disk.c. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/block.c | 34 +- src/block.h | 1 - src/disk.c | 32 3 files changed, 33 inse

Re: [SeaBIOS] Build failed in Jenkins: seabios #220

On Wed, Mar 30, 2016 at 07:50:33PM +0200, Jenkins Build Host wrote: > See > > Changes: > > [kevin] Support for booting from LSI Logic LSI53C1030, SAS1068, SAS1068e [...] > Compile checking out/src/hw/mpt-scsi.o > src/hw/mpt-scsi.c:

Re: [SeaBIOS] [PATCH v2] Support for booting from LSI Logic LSI53C1030, SAS1068, SAS1068e

On Tue, Mar 29, 2016 at 03:11:06PM +0200, Paolo Bonzini wrote: > On 29/03/2016 14:43, Kevin O'Connor wrote: > >> > Also known as Fusion MPT disk; this controller model is supported > >> > by VirtualBox and VMware, and QEMU support patches have been > >> &g

Re: [SeaBIOS] [PATCH v2] Support for booting from LSI Logic LSI53C1030, SAS1068, SAS1068e

On Fri, Mar 25, 2016 at 05:04:31PM +0100, Paolo Bonzini wrote: > From: Don Slutz > > Also known as Fusion MPT disk; this controller model is supported > by VirtualBox and VMware, and QEMU support patches have been > posted. Thanks Paolo. The patch didn't apply - I took a

Re: [SeaBIOS] [PATCH] sdcard: abort controller setup if capabilities invalid

On Wed, Mar 16, 2016 at 08:53:09PM -0500, Matt DeVillier wrote: > If the version and low/high capabilities flags of a sdcard controller are > invalid (0x), assume the controller address is invalid, and exit setup > before attempting to reset the controller, which would introduce an >

Re: [SeaBIOS] [patch v2 - reformatted] sdcard: skip detection of PCI sdhci controllers if etc/sdcard used

Therefore, if > the CBFS contains etc/sdcard entries, skip detection of any visible PCI > sdhci controllers in order to avoid duplicate entries in the boot menu. > > patch implementation suggested by Kevin O'Connor :) > > Signed-off-by: Matt DeVillier <matt.devill...@gmail.com> T

Re: [SeaBIOS] [PATCH] coreboot: Add support for FMAP and multiple CBFS

On Thu, Mar 10, 2016 at 11:11:59AM -0600, Ben Gardner wrote: > Hi Kevin, > > I plan to have the default CBFS contain only coreboot and SeabIOS and > a few payloads (coreinfo, memtest86, PXE) that I don't intend to > change often. > That would be protected with a hash and would be kept small for >

Re: [SeaBIOS] [PATCH] coreboot: Add support for FMAP and multiple CBFS

On Wed, Mar 09, 2016 at 12:19:43PM -0600, Ben Gardner wrote: > ROM images with a FMAP may have multiple CBFS. > Scan all available CBFS so that, say, a SeaBIOS bootable image doesn't > have to be in the main CBFS. > > Coreboot puts the FMAP location in the BOOT_MEDIA_PARAMS entry in the >

Re: [SeaBIOS] [patch] sdcard: skip detection of PCI sdhci controllers if etc/sdcard used

On Thu, Mar 10, 2016 at 12:38:14AM -0600, Matt DeVillier wrote: > Some BayTrail ChromeOS devices have the eMMC controller hidden (thus > requiring the use of etc/sdcard), while others do not, making it problematic > to have a single payload which serves all devices properly. Therefore, if > the

Re: [SeaBIOS] [PATCH V2] fw/pci: add Q35 S3 support

On Tue, Mar 01, 2016 at 04:06:45PM +0200, Marcel Apfelbaum wrote: > Following the i440fx example, save the LPC, SMBUS and PCIEXBAR bdfs > between OS sleeps and use them to re-configure the > corresponding registers. Thanks. I committed this patch. -Kevin

Re: [SeaBIOS] [PATCH] ahci: set transfer mode according to the capabilities of connected drive

On Sat, Feb 20, 2016 at 03:20:15PM +0100, Gerd Hoffmann wrote: > Use case: cf cards behind sata-ide bridge, which might not support > the default transfer mode. > > Based on a patch by Werner Zeh , > with some minor tweaks applied. > > Signed-off-by: Gerd Hoffmann

Re: [SeaBIOS] [PATCH 2/2] tpm: Write logs in TPM 2 format

On Fri, Feb 26, 2016 at 01:28:14PM -0500, Stefan Berger wrote: > On 02/23/2016 11:53 AM, Kevin O'Connor wrote: > >commit 102648838c0cf640c01b5f092e8f432d8f2abb8f > >Author: Kevin O'Connor <ke...@koconnor.net> > >Date: Fri Feb 5 22:28:17 2016 -0500 > > > &

Re: [SeaBIOS] [PATCH] ld: fix .text section address alignment

On Tue, Feb 23, 2016 at 04:06:20PM +0100, Roger Pau Monné wrote: > El 23/2/16 a les 15:53, Kevin O'Connor ha escrit: > > On Mon, Feb 22, 2016 at 12:07:00PM +0100, Roger Pau Monné wrote: > >> El 20/2/16 a les 3:41, Kevin O'Connor ha escrit: > >>> On Tue, Feb 16, 2016

Re: [SeaBIOS] [PATCH 2/2] tpm: Write logs in TPM 2 format

On Mon, Feb 08, 2016 at 11:36:40AM -0500, Kevin O'Connor wrote: > On Mon, Feb 08, 2016 at 07:25:35AM -0500, Stefan Berger wrote: > > On 02/06/2016 01:35 PM, Kevin O'Connor wrote: > > >Add support for the TPM 2 format of log messages. > > > > > >Write the lo

Re: [SeaBIOS] [RFC PATCH v4] fw/pci: Add support for mapping Intel IGD via QEMU

On Tue, Feb 16, 2016 at 02:39:27PM -0700, Alex Williamson wrote: > QEMU provides two fw_cfg files to support IGD. The first holds the > OpRegion data which holds the Video BIOS Table (VBT). This needs to > be copied into reserved memory and the address stored in the ASL > Storage register of the

Re: [SeaBIOS] [PATCH] ld: fix .text section address alignment

On Mon, Feb 22, 2016 at 12:07:00PM +0100, Roger Pau Monné wrote: > El 20/2/16 a les 3:41, Kevin O'Connor ha escrit: > > On Tue, Feb 16, 2016 at 06:21:10PM +0100, Roger Pau Monné wrote: > >> El 16/2/16 a les 17:33, Kevin O'Connor ha escrit: > >>> On Tue, Feb 16, 2016

Re: [SeaBIOS] [PATCH] ahci: set transfer mode according to the capabilities of connected drive

On Sat, Feb 20, 2016 at 03:20:15PM +0100, Gerd Hoffmann wrote: > Use case: cf cards behind sata-ide bridge, which might not support > the default transfer mode. > > Based on a patch by Werner Zeh , > with some minor tweaks applied. > > Signed-off-by: Gerd Hoffmann

Re: [SeaBIOS] [PATCH] ld: fix .text section address alignment

On Tue, Feb 16, 2016 at 06:21:10PM +0100, Roger Pau Monné wrote: > El 16/2/16 a les 17:33, Kevin O'Connor ha escrit: > > On Tue, Feb 16, 2016 at 01:56:26PM +0100, Roger Pau Monne wrote: > >> According to the output from readelf, the .text section should be aligne

Re: [SeaBIOS] AHCI: Set transfer mode according to the capabilities of connected drive

On Mon, Feb 15, 2016 at 12:00:48PM +, Zeh, Werner wrote: > Hi Kevin. > > We had some issues with some connected AHCI devices in SeaBIOS. We > have connected some CF-Cards by using a simple SATA<->IDE bridge to > the mainboard and in some cases, the drive (which is the CF-card) > was not

Re: [SeaBIOS] [PATCH 1/2] tpm: Unify tpm_fill_hash()/tpm_log_extend_event() and use in BIOS interface

On Mon, Feb 08, 2016 at 07:19:27AM -0500, Stefan Berger wrote: > On 02/06/2016 01:35 PM, Kevin O'Connor wrote: > >Don't call tpm_fill_hash() or tpm_log_extend_event() from any internal > >code (ie, tpm_add_measurement_to_log). The internal code does not > >require

Re: [SeaBIOS] Error while compiling Seabios for Arch Linux ARM

On Thu, Feb 18, 2016 at 05:49:39PM +0200, XJDHDR wrote: > >> Greetings > >>  > >> I am currently trying to compile Seabios for Arch Linux ARM and I've > >> encountered an error during the compilation ‎ > > > >SeaBIOS implements an x86 legacy BIOS. As such, it requires an x86 > >compiler. So, you

Re: [SeaBIOS] Error while compiling Seabios for Arch Linux ARM

On Wed, Feb 17, 2016 at 06:14:25PM +0200, Xavier de Rauville wrote: > Greetings > > I am currently trying to compile Seabios for Arch Linux ARM and I've > encountered an error during the compilation that appears to be caused by a > misconfiguration in the file downloaded from here: >

Re: [SeaBIOS] [Qemu-devel] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Mon, Feb 15, 2016 at 09:29:26PM +0200, Michael S. Tsirkin wrote: > I can build a generic interface to pass addresses > allocated by bios back to QEMU. It looks like this would > be useful for other purposes as well. Interested? If this is undertaken, I suggest extending fw_cfg to support

Re: [SeaBIOS] Chromebook doesn't boot BSD

On Mon, Feb 15, 2016 at 05:16:06PM +0100, Ronny Schneider wrote: > > Am 15.02.2016 um 15:40 schrieb edward wandasiewicz <0.w3...@gmail.com>: > > On Sun, Feb 14, 2016 at 11:02 PM, Kevin O'Connor <ke...@koconnor.net> wrote: > >> - it looks more like the vario

Re: [SeaBIOS] ipxe/seabios: segment register initialization

On Mon, Feb 15, 2016 at 08:43:18AM +0200, Michael S. Tsirkin wrote: > On Mon, Feb 15, 2016 at 01:07:09AM +, Michael Brown wrote: > > On 14/02/16 19:52, Michael S. Tsirkin wrote: > > >On Sun, Feb 14, 2016 at 05:36:38PM +, Michael Brown wrote: > > >>On 14/02/16 15:53, Michael S. Tsirkin

Re: [SeaBIOS] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Sat, Feb 13, 2016 at 06:03:31PM -0700, Alex Williamson wrote: > On Sat, 13 Feb 2016 19:20:32 -0500 > "Kevin O'Connor" <ke...@koconnor.net> wrote: > > This confuses me - why didn't the host system BIOS turn on the LCD > > panel during host bootup? > &g

Re: [SeaBIOS] Chromebook doesn't boot BSD

On Sun, Feb 14, 2016 at 06:04:16PM +0100, Ronny Schneider wrote: > Hello there, > > i have a Toshiba Chromebook 2 (CB30-B-104) with a flashed on SeaBIOS by the > script from John Lewis: > https://johnlewis.ie/custom-chromebook-firmware/rom-download/ > > Linux is running very well but i want to

Re: [SeaBIOS] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Sat, Feb 13, 2016 at 08:12:09AM -0700, Alex Williamson wrote: > On Fri, 12 Feb 2016 21:49:04 -0500 > "Kevin O'Connor" <ke...@koconnor.net> wrote: > > On Fri, Feb 12, 2016 at 05:23:18PM -0700, Alex Williamson wrote: > > > Intel IGD makes use of

Re: [SeaBIOS] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Sat, Feb 13, 2016 at 11:51:51AM -0700, Alex Williamson wrote: > On Sat, 13 Feb 2016 13:18:39 -0500 > "Kevin O'Connor" <ke...@koconnor.net> wrote: > > On Sat, Feb 13, 2016 at 08:12:09AM -0700, Alex Williamson wrote: > > > On Fri, 12 Feb 2016 21:4

Re: [SeaBIOS] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Sat, Feb 13, 2016 at 01:57:09PM -0700, Alex Williamson wrote: > On Sat, 13 Feb 2016 15:05:09 -0500 > "Kevin O'Connor" <ke...@koconnor.net> wrote: > > On Sat, Feb 13, 2016 at 11:51:51AM -0700, Alex Williamson wrote: > > > On Sat, 13 Feb 2016 13:1

Re: [SeaBIOS] [PATCH 2/2] tpm: Write logs in TPM 2 format

On Mon, Feb 08, 2016 at 07:25:35AM -0500, Stefan Berger wrote: > On 02/06/2016 01:35 PM, Kevin O'Connor wrote: > >Add support for the TPM 2 format of log messages. > > > >Write the logs in the format that is appropriate for the version of > >the host's TPM. For TPM

Re: [SeaBIOS] [PATCH 00/14] Clean up PCI BAR handling

On Tue, Feb 02, 2016 at 11:18:43PM -0500, Kevin O'Connor wrote: > This series adds some helper functions for working with PCI BARs (Base > Address Registers), and it then updates all the drivers to use these > helper functions. The new helper functions perform sanity checks on > the B

Re: [SeaBIOS] [PATCH 0/4] Some additional PCI cleanups

On Wed, Feb 03, 2016 at 10:51:50AM -0500, Kevin O'Connor wrote: > Some additional PCI code cleanup - most notable is the first patch > which adds a '%pP' modifier to the 'printf' code for outputting > 'struct pci_device' pointers. FYI, I committed this series

[SeaBIOS] [PATCH 1/2] tpm: Unify tpm_fill_hash()/tpm_log_extend_event() and use in BIOS interface

this function only in the 16bit BIOS interface code. With the code now specific to the BIOS interface it can more easily return a BIOS specific error return code. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/tcgbios.

[SeaBIOS] [PATCH 0/2] tpm2 logging

Hi Stefan, What do you think about something like these two patches in place of your last patch 10? Basically using 'struct tcg_pcr_event2_sha1' instead of introducing a new 'struct log_entry'. -Kevin Kevin O'Connor (2): tpm: Unify tpm_fill_hash()/tpm_log_extend_event() and use in BIOS

Re: [SeaBIOS] [PATCH 1/2] ehci: Only delay UHCI/OHCI port scan until after EHCI setup completes

On Tue, Feb 02, 2016 at 03:03:36PM -0500, Kevin O'Connor wrote: > EHCI controller setup needs to occur prior to checking any UHCI or > OHCI ports to ensure a high speed device is not mistakenly configured > on a full speed "companion" controller. However, only the UHCI/OHC

Re: [SeaBIOS] [PATCH v3 00/11] Add TPM 2 support

On Tue, Feb 02, 2016 at 01:09:08PM -0500, Stefan Berger wrote: > This series of patches adds TPM 2 support to SeaBIOS in the way previously > proposed. Thanks Stefan. I committed patches 1-9 and 11. I wanted to look further at patch 10. -Kevin ___

[SeaBIOS] [PATCH 2/2] tpm: Write logs in TPM 2 format

specification (section 5.3): Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/std/tcg.h | 35 +++ src/tcgbios.c | 76 +++ 2 files changed, 101 insertions(+), 10 deletions(-) diff --git a/src/std/tcg.h b/s

Re: [SeaBIOS] [RFC PATCH v2] fw/pci: Add support for mapping Intel IGD OpRegion via QEMU

On Thu, Feb 04, 2016 at 08:52:44AM +0100, Gerd Hoffmann wrote: > Hi, > > > the same or just use it on the first one we encounter. We're probably > > putting way too much thought into this scenario that Intel likely has no > > expectation of supporting though ;) Thanks, > > Yea, lets stick

Re: [SeaBIOS] [RFC PATCH v2] fw/pci: Add support for mapping Intel IGD OpRegion via QEMU

On Wed, Feb 03, 2016 at 02:38:47PM -0700, Alex Williamson wrote: > On Wed, 2016-02-03 at 12:43 -0700, Alex Williamson wrote: > > On Wed, 2016-02-03 at 10:04 +0100, Gerd Hoffmann wrote: > > >   Hi, > > >   > > > > +static void intel_igd_opregion_setup(struct pci_device *dev, void *arg) > > > > +{ >

[SeaBIOS] [PATCH 2/4] pci: Move code in pci.c that is specific to pciinit.c to pciinit.c

Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/fw/mtrr.c| 1 - src/fw/pciinit.c | 37 + src/hw/pci.c | 26 -- src/hw/pci.h | 15 --- src/util.h | 2 ++ 5 files changed, 39 insertions(

[SeaBIOS] [PATCH 0/4] Some additional PCI cleanups

Some additional PCI code cleanup - most notable is the first patch which adds a '%pP' modifier to the 'printf' code for outputting 'struct pci_device' pointers. This series is on top of the previous series; it is also at: https://github.com/KevinOConnor/seabios/tree/testing -Kevin Kevin

[SeaBIOS] [PATCH 4/4] scsi: Always use MAXDESCSIZE when building drive description

Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/esp-scsi.c | 2 +- src/hw/lsi-scsi.c | 2 +- src/hw/megasas.c | 3 ++- src/hw/pvscsi.c | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/hw/esp-scsi.c b/src/hw/esp-scsi.c index 086a032..c98989c

[SeaBIOS] [PATCH 2/2] usb: Eliminate USB controller setup thread

There are no longer any sleep or yield calls during the usb controller device scans, so there is no need to run these device scans in a separate thread. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/usb-ehci.c | 1 - src/hw/usb-ohci.c | 1 - src/hw/usb-uhci.c | 1 - src/

[SeaBIOS] [PATCH 1/2] ehci: Only delay UHCI/OHCI port scan until after EHCI setup completes

ange moves back the ehci controller setup check until port scan in UHCI/OHCI. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/usb-ehci.c | 8 ++-- src/hw/usb-ehci.h | 1 + src/hw/usb-ohci.c | 3 +++ src/hw/usb-uhci.c | 4 4 files changed, 14 insertions(+), 2 deletion

[SeaBIOS] [PATCH 02/14] ahci: Convert to new PCI BAR helper functions

IO accesses to the device. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/ahci.c | 35 --- src/hw/ahci.h | 3 +-- 2 files changed, 17 insertions(+), 21 deletions(-) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 83b747c..5401cca 100644 ---

[SeaBIOS] [PATCH 00/14] Clean up PCI BAR handling

ive driver for. This series is also available at: https://github.com/KevinOConnor/seabios/tree/testing -Kevin Kevin O'Connor (14): pci: Add helper functions for internal driver BAR handling ahci: Convert to new PCI BAR helper functions ata: Convert to new PCI BAR helper functions esp-s

[SeaBIOS] [PATCH 04/14] esp-scsi: Convert to new PCI BAR helper functions

Use the pci_enable_x() functions. The esp-scsi controller code will now explicitly set PCI_COMMAND_IO instead of assuming it has already been enabled. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/esp-scsi.c | 13 ++--- 1 file changed, 6 insertions(+), 7 del

[SeaBIOS] [PATCH 08/14] sdcard: Convert to new PCI BAR helper functions

Use the pci_enable_x() functions. After this change, the sdcard driver will no longer enable PCI_COMMAND_IO or PCI_COMMAND_MASTER accesses, as the sdcard driver doesn't actually use IO BARs or implement DMA. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/sdcard.

[SeaBIOS] [PATCH 09/14] ehci: Convert to new PCI BAR helper functions

Use the pci_enable_x() functions. The ehci controller code will now explicitly set PCI_COMMAND_MEMORY instead of assuming it has already been enabled. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/usb-ehci.c | 12 ++-- 1 file changed, 6 insertions(+), 6 del

[SeaBIOS] [PATCH 03/14] ata: Convert to new PCI BAR helper functions

Use the pci_enable_x() functions. The ATA controller code will now explicitly set PCI_COMMAND_IO instead of assuming it has already been enabled. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/ata.c | 25 - 1 file changed, 12 insertions(+), 13 del

[SeaBIOS] [PATCH 13/14] virtio: Convert to new PCI BAR helper functions

ead of assuming it has already been enabled. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/virtio-pci.c | 36 src/hw/virtio-pci.h | 32 ++-- 2 files changed, 38 insertions(+), 30 deletions(-) diff --git a/src/

[SeaBIOS] [PATCH 07/14] pvscsi: Convert to new PCI BAR helper functions

Use the pci_enable_x() functions. The pvscsi controller code will now explicitly set PCI_COMMAND_MEMORY instead of assuming it has already been enabled. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/pvscsi.c | 17 - 1 file changed, 8 insertions(+), 9 del

[SeaBIOS] [PATCH 11/14] uhci: Convert to new PCI BAR helper functions

Use the pci_enable_x() functions. The uhci controller code will now explicitly set PCI_COMMAND_IO instead of assuming it has already been enabled. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/usb-uhci.c | 16 +--- 1 file changed, 9 insertions(+), 7 del

[SeaBIOS] [PATCH 12/14] xhci: Convert to new PCI BAR helper functions

Use the pci_enable_x() functions. The xhci controller code will now explicitly set PCI_COMMAND_MEMORY instead of assuming it has already been enabled. Signed-off-by: Kevin O'Connor <ke...@koconnor.net> --- src/hw/usb-xhci.c | 27 ++- 1 file changed, 14 insertions(

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