On 08/03/2012 12:01 AM, Iztok Jeras wrote:
> I would also like to know, if there are any plans for the next
> features, before I start bothering you with all my ideas (I am really
> excited about being part of this project):
> - continuous sampling mode
Yes, this is already supported. The FX2-bas
Hi,
I updated the link and network layer code this weekend. Regarding all
the timing options I decided not to document them, this should be
acceptable, since the defaults are god for most cases (99%). You will
probably have to do some white-space cleanup (not much), but otherwise
the code should b
Hi,
The recoded link layer PD is now working. But I still have to clean up
the list of options (I added all protocol timing, although only some
are used). Overdrive support is now tested and works. There is no need
to merge the code now, unless you would like to make a release soon,
than I would s
Hi,
My replays are inline.
Regards,
Iztok Jeras
On Sun, Jul 22, 2012 at 3:08 AM, Uwe Hermann wrote:
> Hi,
>
> On Tue, Jul 17, 2012 at 10:15:41PM +0200, Iztok Jeras wrote:
>> First, I followed suggestions regarding rebase of git commits and
>> using the 'onewire' branch instead of 'master'. Coul
Hi,
On Tue, Jul 17, 2012 at 10:15:41PM +0200, Iztok Jeras wrote:
> First, I followed suggestions regarding rebase of git commits and
> using the 'onewire' branch instead of 'master'. Could you check if I
> did it correctly.
> https://github.com/jeras/sigrok
Yep, looks good, thanks! I merged the c
Hi,
First, I followed suggestions regarding rebase of git commits and
using the 'onewire' branch instead of 'master'. Could you check if I
did it correctly.
https://github.com/jeras/sigrok
I now separated the link/network/transport layers into separate
protocols, overdrive mode detection is now d
Hi,
I found one example device not supporting the 'network layer' is
DS1821, so it makes sense to split the PD into the link and network
layer. I will duplicate the related overdrive code, and use the
overdrive decoder option to disable overdrive detection by the
protocol. This way all devices sho
Hi Uwe,
Comments are inline.
Regards, Iztok Jeras
On Wed, Jul 4, 2012 at 2:20 AM, Uwe Hermann wrote:
> Hi,
>
> On Tue, Jul 03, 2012 at 12:33:17AM +0200, Iztok Jeras wrote:
>> The 1-Wire protocol decoder should be almost ready now, this week I
>> will add some more dumps and test the decoder wit
Hi,
On Tue, Jul 03, 2012 at 12:33:17AM +0200, Iztok Jeras wrote:
> The 1-Wire protocol decoder should be almost ready now, this week I
> will add some more dumps and test the decoder with them. The code is
> ready for a first review, next issues remain:
Thanks, merged for now with a few minor cha
Hi,
The 1-Wire protocol decoder should be almost ready now, this week I
will add some more dumps and test the decoder with them. The code is
ready for a first review, next issues remain:
1. Annotations:
Currently there are 3 annotation options, for three protocol layers
(link, network, transport),
Hi,
I found the issue with missing annotations in my decoder. I should be
able to remove the debug code now.
Regards,
Iztok Jeras
On Sat, Jun 23, 2012 at 1:37 PM, Iztok Jeras wrote:
> Hi,
>
> I now have a few 1-Wire dumps ready, but the whole protocol (lower
> layers) is not yet covered, overdr
Hi,
I now have a few 1-Wire dumps ready, but the whole protocol (lower
layers) is not yet covered, overdrive mode is missing. It will be hard
to cover all the higher level protocol elements, I should be able to
add some more dumps, once I understand the higher protocol layers
better. I should be a
On 05/22/2012 11:09 PM, Iztok Jeras wrote:
> $ sigrok-cli -i onewire.bin -I binary -p 1=OWR -o onewire.sr
> The problem with the output file is that it is missing a sample rate.
> How could I specify it?
> https://github.com/jeras/sigrok-dump/tree/master/onewire/verilog
As Uwe said, the binary in
Hi,
and welcome :)
On Tue, May 22, 2012 at 11:09:18PM +0200, Iztok Jeras wrote:
> Dumps:
>
> I have access to a logic analyzer at work, and I have a USB/UART based
> 1-Wire master, and the FPGA based master mentioned above. I also have
> several 1-Wire devices (thermometers, ADC, GPIO, memory).
Hi,
Let me introduce myself first. I am an ASIC developer (Verilog coder)
from Ljubljana (Slovenia). A prof of my 1-Wire experience here is my
1-Wire master written in Verilog, with a port of the original Dallas
Semiconductors software (everything was tested on a FPGA):
https://github.com/jeras/so
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