to
Petr Hluzín in the same thread?
No. just a slow writer.
I'd thought perhaps that you had linked by hand.
The if at all was because of the thought that you might have run the .o file.
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or avr-gcc?
My suspicion is that for some reason you do not have the C runtime.
How, if at all, did you link?
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interface. As I remember, Joel
Sherrill has used this for running multicore simulation. Maybe he can
answer your questions for TCL interface.
IIRC, the TCL and the python create the proper
Net objects before starting the simulation.
That can be done in C++.
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not causing actual worry,
it will still be an annoying example of ignorance.
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.
That would depend on whether the kludges have to be coded once
where users don't have to look at them or users have to code kludges.
[1] http://lists.nongnu.org/archive/html/simulavr-devel/2010-03/msg00037.html
- or 38? (Guessing. The list lags behind)
37 is correct.
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.
At the time, I was too distracted by my war with git to look closely,
but my recollection is that they were fairly major.
Bug fixes and additional features I have no problem with.
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the existing
CVS repo into an SVN one, just tell me so. I've already migrated two
repos (avrdude and avr-libc), so I know how this works on savannah.
This one would much prefer subversion to renewing his war with git.
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To git, what is a branch? What is a working tree?
The documentation I've read seems to assume that these are things that everyone
knows.
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On Sat Jan 23 12:41 , henne...@cableone.net sent:
On Sat Jan 23 12:27 , henne...@cableone.net sent:
To git, what is a branch? What is a working tree?
Also merge?
I have a clue about merge now,
but I have yet to see a single .c or .h file from a git repository.
If checkout is supposed to do
simulavr and simulavrxx into the same repository?
I can't figure out how to check anything out.
It seems to be in the same state as my previous effort.
See attachment.
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simulavrxx
IIRC the desired repository would have both branches.
By itself, simulavrxx would not be enough.
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On Sun Jan 3 12:55 , henne...@cableone.net sent:
On Wed Dec 29 6:05 , ThomasK sent:
Fedora 11 seems not to believe in cvs2git.
I've not been able to find the magic words to make git itself
convert both simulavr and simulavrxx.
The magic word, resp. command should be git help cvsimport
rewriting the From: header.
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On Wed Dec 23 10:36 , Klaus Rudolph sent:
henne...@cableone.net schrieb:
On Wed Dec 23 2:39 , Klaus Rudolph sent:
Petr Hluzín schrieb:
2009/12/22 Knut Schwichtenberg ksc...@web.de:
In one of my previous projects I used a 2^22Hz crystal. The
frequency is 4.194304MHz. So
or JTAG:
An assert that depends on the values of registers in more than one cpu.
An assert that takes zero time to calculate.
I want to be able to connect simulated cpus
to simulated hardware of my own design.
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On Mon Oct 12 13:25 , Joel Sherrill sent:
henne...@cableone.net wrote:
I don't quite know what I'm doing.
The conversion tools want a local repository.
I eventually tried to get one with this command:
rsync -av cvs.sv.nongnu.org::sources/simulavr/ .
From the files listed, I thought I'd
git: 'cvsimport' is not a git-command. See 'git --help'.
git --help doesn't.
git: 'cvs-import' is not a git-command. See 'git --help'.
Now what?
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On Wed Sep 30 10:51 , henne...@cableone.net sent:
IIRC, for one who knows what he is doing,
conversion from CVS to subversion or git is trivial.
I don't quite know what I'm doing.
The conversion tools want a local repository.
I eventually tried to get one with this command:
rsync -av
of the current
CVS repo on your machine and make an announcement?
Once that is done, the discussion can be in terms
of what we want instead of how hard it is to get it.
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the savannah code and the Onno code use
the same regression test organization?
IIRC the Onno code uses a different port register
access syntax from the savannah code.
If so, I'd like a discussion about whether
to commit it to the savannah code.
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is tangled with
the question of what code from github we want to keep.
I want them to not be tangled.
While I suspect git of greatness, whether we use it should
not depend on how much we like the code on github.
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whether Onno made changes to the regression testing
organization.
I do remember that even though it did,
the Makefile seemed to me to have no way to invoke the testing mechanism.
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them in the
tracker is a PITA. This is another reason why I'm using git now.
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a central point to attach
tracing probes to the I/O parts of the simulator.
I remember being dubious about this, but I can look at it again.
Removing redundant code is important.
Code that isn't there doesn't need testing.
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sense. There's nobody else who is willing and able to do
the work on your behalf. It's a VCS, so whatever happens, it can
always be rolled back when really needed.
OK.
I'll try not to let the smoke out of Savannah.
At work, I only get to mess up my own repository.
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to build it, look around, what's
there ... and send your questions to mailing list! ;-)
I would really like some word from the simulavr maintainers.
Is there a reason that the official repository
and Onno's git repository are still not in sync?
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version?
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for IOReg, which hasn't only byte getter/setter, but also
a special bit setter functionality. (get would work in every case)
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git repo is git repo?
I expect to need to use git eventually,
so what is the best way to make progress?
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On Tue Aug 18 13:38 , henne...@cableone.net sent:
On Tue Aug 18 11:47 , ThomasK nongnu@sce-gbr.de sent:
Behaviour in simulavr is now like in M128, means read complete byte,
modify, write complete byte. For the new behaviour we need a new
interface for IO registers, one is clearBit(bitnum
On Wed Aug 19 8:15 , 'henne...@cableone.net' henne...@cableone.net sent:
On Tue Aug 18 13:38 , henne...@cableone.net sent:
On Tue Aug 18 11:47 , ThomasK nongnu@sce-gbr.de sent:
Behaviour in simulavr is now like in M128, means read complete byte,
modify, write complete byte. For the new
On Wed Aug 19 8:15 , henne...@cableone.net sent:
On Tue Aug 18 13:38 , henne...@cableone.net sent:
On Tue Aug 18 11:47 , ThomasK nongnu@sce-gbr.de sent:
Behaviour in simulavr is now like in M128, means read complete byte,
modify, write complete byte. For the new behaviour we need a new
also some other nice features, which
change the behaviour of core?
There are some registers that affect flags by being read,
but I think those are out of the range of SBI, CBI, SBIC and SBIS.
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On Mon Aug 17 13:25 , ThomasK sent:
henne...@cableone.net schrieb:
Also, after some thought, I realized that my toggle
code would fail for SBI and CBI instructions.
It's probable that the original SBI and CBI
code would fail on the atmega{48,88,168}s.
On the atmega128, SBI and CBI
My original sandbox was cvs0710 .
I cp -r'ed it to cp0710 .
From cp0710, cvs diff takes about a minute to produce any output.
From cvs0710, cvs diff starts in about a second.
Any idea why?
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seems to depend on check-recursive
which I can't find anywhere.
In regress/test_opcodes, check depends on check-am
which depends on all-am which depends on Makefile.
???
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On Sat Jul 11 20:22 , henne...@cableone.net sent:
Here is the promised refactoring of the atmega{48,88,18} code.
Oops. atmega{48,88,168}
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lines at the beginning.
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hwmega668extirq.h
Description: Binary data
refactor.patch
Description: Binary data
hwmega668extirq.cpp
Description: Binary data
On Thu Jul 9 22:55 , henne...@cableone.net sent:
The attached code should implement atmega88 and atmega168.
It hasn't been tested much.
It compiles and the result still passes make check .
The attached patch is obviously incomplete.
I've attached the missing files.
atmega668base.{cpp,h
On Fri Jul 10 9:54 , Joel Sherrill sent:
henne...@cableone.net wrote:
On Thu Jul 9 22:55 , henne...@cableone.net sent:
The attached code should implement atmega88 and atmega168.
It hasn't been tested much.
It compiles and the result still passes make check .
The attached patch
On Thu Jul 9 9:04 , Joel Sherrill sent:
henne...@cableone.net wrote:
/usr/bin/swig -c++ -python -I/usr/include/python2.5 -o pysimulavr_wrap.cpp
../../cvs0708up/src/pysimulavr.i
../../cvs0708up/src/rwmem.h:48: Warning(362): operator= ignored
../../cvs0708up/src/rwmem.h:52
I edited bootstrap so that I could tell where messages were coming from.
The *.stdout files were all empty.
I've attached bootstrap and the others.
diff and grep tell me that the cache complaints are all the same.
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since I did any development on it.
A possibly better-made linux box has 2.5.2 .
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happened.
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files.
I even left the erroneous copyrights alone.
The patch subsumes the three-in-one patch.
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atmega168.h
Description: Binary data
atmega668base.cpp
Description
On Wed Jul 8 11:40 , Joel Sherrill sent:
henne...@cableone.net wrote:
On Tue Jul 7 9:10 , 'henne...@cableone.net' henne...@cableone.net sent:
I'm home.
I've attached src/Makefile.am and the result of
cvs diff -c in the root.
The Makefile.am has atmega668*. I thought you were
/dev/null to the files added to
src/Makefile.am so I could build like you would.
Built fine for me after a bootstrap on Fedora 10.
I hope this helps some. :)
--joel
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On Wed Jul 8 11:54 , henne...@cableone.net sent:
On Wed Jul 8 11:40 , Joel Sherrill sent:
Other projects have had users encounter this. I found
this URL: http://trac.mcs.anl.gov/projects/mpich2/ticket/20
I took a quick look at this. Looks like autoconf-2.62 expects cached
variables
On Wed Jul 8 20:03 , henne...@cableone.net sent:
On Wed Jul 8 11:54 , henne...@cableone.net sent:
On Wed Jul 8 11:40 , Joel Sherrill sent:
Other projects have had users encounter this. I found
this URL: http://trac.mcs.anl.gov/projects/mpich2/ticket/20
I took a quick look
such. But this wouldn't be needed to compile and link
all. pkginclude_HEADERS is needed for building installation or
distribution. Not for building program.
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On Tue Jul 7 9:10 , 'henne...@cableone.net' henne...@cableone.net sent:
On Tue Jul 7 8:51 , ThomasK sent:
You have appended Makefile.am from root directory. But to compile your
Arrrg. I grabbed the wrong Makefile.am .
I'll have to get home to find the right one.
I'm home.
I've attached
that --enable-python was not a recognized
option.
--enable-tcl was ok.
After moving autom4te.cache, I tried again.
Same result.
I've attached the new Makefile.am .
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I'm working on it.
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think that there might be an incantation to make it work,
but I don't remember the incantation.
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executable in python.
I'm working on it, but my C++/python expertise isn't yet.
The swig site looks like it might be more helpful than my Programming Python
book.
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Should I have submitted the patch through a different mechanism?
On Sun Jun 14 16:05 , henne...@cableone.net sent:
Index: bootstrap
===
RCS file: /sources/simulavr/simulavrxx/bootstrap,v
retrieving revision 1.8
diff -u -r1.8
a requirement.
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, the following commands succeeded:
../cvs0605/configure --prefix=/usr/local/sim --enable-tcl --enable-python
make
make check
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Is bootstrap idempotent, i.e. does running it
twice have the same effect as running it once?
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faster.
For folks like me, it would save some fear and uncertainty,
not to mention doubt, if a patch's documentation explicitly mentioned
its p-level and the directory from which it was to be applied.
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configure:20369: checking for python = 2.1.1
_cv_python_211=yes
SWIG_PYTHON_OPT='-python'
Note the python value from configure.
[henne...@localhost b0605]$ which python
/usr/bin/python
What is going on?
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On Wed Jun 3 13:39 , Joerg Wunsch sent:
As henne...@cableone.net wrote:
Does this mean I should add an allowed issuer?
Yes. Their server certificate is signed by CAcert.org, a
volunteer-based root CA.
If so, how?
Please go here:
http://www.cacert.org/index.php\?id=3
and install
do have a CVS backup, do you?
My most recent intact copy is from March.
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...@cvs.savannah.nongnu.org:/sources/simulavr co
simulavrxx
It worked on my previous checkout.
I don't have a strong care about the revision control
system. Retraining me should still be possible. :)
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What's happening with cvs.savannah.nongnu.org ?
I haven't been able to checkout from there yesterday or today.
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/usr/include
AVR_TCL_LIB = -L/usr/lib -ltcl8.5
My avr-specific stuff is not in /usr/include or in /usr/lib .
Does that need fixing? If so, how?
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could be mostly eliminated.
I think it would just have to assign the stack pointer.
The linker script would need to be changed.
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pointer could be made so that it had to be
initialized and so that its destructor deleted its target.
That said, adding a level of indirection will slow things down a bit.
BTW the simulator is not an embedded program.
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On Sat Apr 11 17:34 , Michael N. Moran sent:
henne...@cableone.net wrote:
What reasons for avoiding pointers apply to the
atmega48 that do not apply to the atmega128?
If pointers are useful,
two of the reasons for avoiding them could be avoided with smart pointers.
I assume that you mean
isn't even noticing the other,
these little details don't matter much.
The CPU frequency (400) is set in one place in the
Makefile.am and passed to both the simulator run and the
build.
Is the parity the same?
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of the idea was that having a wrong version would cause some noise.
FWIW if anacomp still has that you are not running the CVS head.
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On Wed Apr 1 15:01 , Knut Schwichtenberg sent:
henne...@cableone.net wrote:
According to my man cvs, head is the default.
head != HEAD?
How do I get HEAD?
If I look with the web interface into the CVS, I see CVS Tags: HEAD.
Until now I always used
cvs -d:pserver:anonym...@cvs.sv.gnu.org
want to make sure my understanding matches
what the reality is.
Does that mean that there will be steps taken to ensure that
the data format sent matches the data format expected?
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On Wed Apr 1 17:27 , Joel Sherrill sent:
henne...@cableone.net wrote:
If, for example, the UART is set to send 7-bit chunks,
but the receiver is expecting 8-bit chunks,
the byte-probe simulation might work even
if the real thing wouldn't have a chance.
IIRC parity and endian mismatches
to nasal demons.
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