CVS commit: src/sys/dev/pci

2021-10-27 Thread Shoichi YAMAGUCHI
Module Name:src Committed By: yamaguchi Date: Thu Oct 28 01:36:43 UTC 2021 Modified Files: src/sys/dev/pci: if_vioif.c virtio.c virtio_pci.c virtiovar.h Log Message: virtio: stop reinit for safety when a device resetting is failed To generate a diff of this commit: cvs

CVS commit: src/sys/dev/pci

2021-10-27 Thread Shoichi YAMAGUCHI
Module Name:src Committed By: yamaguchi Date: Thu Oct 28 01:36:43 UTC 2021 Modified Files: src/sys/dev/pci: if_vioif.c virtio.c virtio_pci.c virtiovar.h Log Message: virtio: stop reinit for safety when a device resetting is failed To generate a diff of this commit: cvs

CVS commit: src/sys/arch/hppa/hppa

2021-10-27 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Wed Oct 27 21:42:58 UTC 2021 Modified Files: src/sys/arch/hppa/hppa: locore.S Removed Files: src/sys/arch/hppa/hppa: sigcode.S Log Message: @thorpej wrote that sigcontext was never used on hppa; remove kernel handling

CVS commit: src/sys/arch/hppa/hppa

2021-10-27 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Wed Oct 27 21:42:58 UTC 2021 Modified Files: src/sys/arch/hppa/hppa: locore.S Removed Files: src/sys/arch/hppa/hppa: sigcode.S Log Message: @thorpej wrote that sigcontext was never used on hppa; remove kernel handling

CVS commit: src/lib/libc/net

2021-10-27 Thread Nia Alarie
Module Name:src Committed By: nia Date: Wed Oct 27 19:24:38 UTC 2021 Modified Files: src/lib/libc/net: getaddrinfo.c Log Message: getaddrinfo(3): malloc + memset -> calloc To generate a diff of this commit: cvs rdiff -u -r1.120 -r1.121 src/lib/libc/net/getaddrinfo.c

CVS commit: src/lib/libc/net

2021-10-27 Thread Nia Alarie
Module Name:src Committed By: nia Date: Wed Oct 27 19:24:38 UTC 2021 Modified Files: src/lib/libc/net: getaddrinfo.c Log Message: getaddrinfo(3): malloc + memset -> calloc To generate a diff of this commit: cvs rdiff -u -r1.120 -r1.121 src/lib/libc/net/getaddrinfo.c

CVS commit: src/sys/arch/x86/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 19:04:04 UTC 2021 Modified Files: src/sys/arch/x86/pci: dwiic_pci.c Log Message: Add more Jasper Lake and Elkhart Lake devices. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8

CVS commit: src/sys/arch/x86/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 19:04:04 UTC 2021 Modified Files: src/sys/arch/x86/pci: dwiic_pci.c Log Message: Add more Jasper Lake and Elkhart Lake devices. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8

CVS commit: [netbsd-8] src/sys/net

2021-10-27 Thread Martin Husemann
Module Name:src Committed By: martin Date: Wed Oct 27 18:52:51 UTC 2021 Modified Files: src/sys/net [netbsd-8]: if_ethersubr.c Log Message: Fix merge mishap from previous (ticket #1704) To generate a diff of this commit: cvs rdiff -u -r1.242.6.8 -r1.242.6.9

CVS commit: [netbsd-8] src/sys/net

2021-10-27 Thread Martin Husemann
Module Name:src Committed By: martin Date: Wed Oct 27 18:52:51 UTC 2021 Modified Files: src/sys/net [netbsd-8]: if_ethersubr.c Log Message: Fix merge mishap from previous (ticket #1704) To generate a diff of this commit: cvs rdiff -u -r1.242.6.8 -r1.242.6.9

CVS commit: src/sys/dev/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 18:50:57 UTC 2021 Modified Files: src/sys/dev/pci: ichsmb.c Log Message: Add Elkhart Lake support. To generate a diff of this commit: cvs rdiff -u -r1.74 -r1.75 src/sys/dev/pci/ichsmb.c Please note that diffs are

CVS commit: src/sys/dev/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 18:50:57 UTC 2021 Modified Files: src/sys/dev/pci: ichsmb.c Log Message: Add Elkhart Lake support. To generate a diff of this commit: cvs rdiff -u -r1.74 -r1.75 src/sys/dev/pci/ichsmb.c Please note that diffs are

CVS commit: src/sys/dev/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 18:26:06 UTC 2021 Modified Files: src/sys/dev/pci: pcidevs.h pcidevs_data.h Log Message: Regen. To generate a diff of this commit: cvs rdiff -u -r1.1426 -r1.1427 src/sys/dev/pci/pcidevs.h cvs rdiff -u -r1.1425

CVS commit: src/sys/dev/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 18:25:31 UTC 2021 Modified Files: src/sys/dev/pci: pcidevs Log Message: Add Intel Elkhart Lake devices. To generate a diff of this commit: cvs rdiff -u -r1.1441 -r1.1442 src/sys/dev/pci/pcidevs Please note that

CVS commit: src/sys/dev/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 18:25:31 UTC 2021 Modified Files: src/sys/dev/pci: pcidevs Log Message: Add Intel Elkhart Lake devices. To generate a diff of this commit: cvs rdiff -u -r1.1441 -r1.1442 src/sys/dev/pci/pcidevs Please note that

CVS commit: src/sys/arch/powerpc/include

2021-10-27 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Wed Oct 27 18:20:23 UTC 2021 Modified Files: src/sys/arch/powerpc/include: pcb.h Log Message: Need frame.h To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/powerpc/include/pcb.h Please note that

CVS commit: src/sys/arch/powerpc/include

2021-10-27 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Wed Oct 27 18:20:23 UTC 2021 Modified Files: src/sys/arch/powerpc/include: pcb.h Log Message: Need frame.h To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/powerpc/include/pcb.h Please note that

CVS commit: src/sys/arch/powerpc/include

2021-10-27 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Wed Oct 27 18:20:08 UTC 2021 Modified Files: src/sys/arch/powerpc/include: signal.h Log Message: There is no sigcontext in ppc64 To generate a diff of this commit: cvs rdiff -u -r1.24 -r1.25

CVS commit: src/sys/arch/powerpc/include

2021-10-27 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Wed Oct 27 18:20:08 UTC 2021 Modified Files: src/sys/arch/powerpc/include: signal.h Log Message: There is no sigcontext in ppc64 To generate a diff of this commit: cvs rdiff -u -r1.24 -r1.25

CVS commit: src/distrib/sets/lists/comp

2021-10-27 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Wed Oct 27 18:19:12 UTC 2021 Modified Files: src/distrib/sets/lists/comp: shl.mi Log Message: fix pic build To generate a diff of this commit: cvs rdiff -u -r1.348 -r1.349 src/distrib/sets/lists/comp/shl.mi Please note that

CVS commit: src/distrib/sets/lists/comp

2021-10-27 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Wed Oct 27 18:19:12 UTC 2021 Modified Files: src/distrib/sets/lists/comp: shl.mi Log Message: fix pic build To generate a diff of this commit: cvs rdiff -u -r1.348 -r1.349 src/distrib/sets/lists/comp/shl.mi Please note that

CVS commit: src/sys/compat/linux

2021-10-27 Thread Jason R Thorpe
Module Name:src Committed By: thorpej Date: Wed Oct 27 16:40:05 UTC 2021 Modified Files: src/sys/compat/linux/arch/amd64: linux_machdep.c src/sys/compat/linux/common: linux_signal.c Log Message: Use __SIGTRAMP_SIGCODE_VERSION rather than hard-coding 0. To

CVS commit: src/sys/compat/linux

2021-10-27 Thread Jason R Thorpe
Module Name:src Committed By: thorpej Date: Wed Oct 27 16:40:05 UTC 2021 Modified Files: src/sys/compat/linux/arch/amd64: linux_machdep.c src/sys/compat/linux/common: linux_signal.c Log Message: Use __SIGTRAMP_SIGCODE_VERSION rather than hard-coding 0. To

CVS commit: src/sys/arch/x86/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 14:53:12 UTC 2021 Modified Files: src/sys/arch/x86/pci: dwiic_pci.c Log Message: Add many Intel I2C devices. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/x86/pci/dwiic_pci.c Please note

CVS commit: src/sys/arch/x86/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 14:53:12 UTC 2021 Modified Files: src/sys/arch/x86/pci: dwiic_pci.c Log Message: Add many Intel I2C devices. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/x86/pci/dwiic_pci.c Please note

CVS commit: src/external/cddl/osnet/dist/lib/libzpool/common

2021-10-27 Thread Simon Burge
Module Name:src Committed By: simonb Date: Wed Oct 27 11:35:23 UTC 2021 Modified Files: src/external/cddl/osnet/dist/lib/libzpool/common: kernel.c Log Message: Hacks to get zdb working on NetBSD: - Force accessing raw device but we're passed the block device. - Deal

CVS commit: src/external/cddl/osnet/dist/lib/libzpool/common

2021-10-27 Thread Simon Burge
Module Name:src Committed By: simonb Date: Wed Oct 27 11:35:23 UTC 2021 Modified Files: src/external/cddl/osnet/dist/lib/libzpool/common: kernel.c Log Message: Hacks to get zdb working on NetBSD: - Force accessing raw device but we're passed the block device. - Deal

CVS commit: src/lib/libc/time

2021-10-27 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Wed Oct 27 11:27:26 UTC 2021 Modified Files: src/lib/libc/time: localtime.c Log Message: fix problem with uninitialized variable on malformed 32 bit time. To generate a diff of this commit: cvs rdiff -u -r1.124 -r1.125

CVS commit: src/lib/libc/time

2021-10-27 Thread Christos Zoulas
Module Name:src Committed By: christos Date: Wed Oct 27 11:27:26 UTC 2021 Modified Files: src/lib/libc/time: localtime.c Log Message: fix problem with uninitialized variable on malformed 32 bit time. To generate a diff of this commit: cvs rdiff -u -r1.124 -r1.125

CVS commit: src/sys/dev/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 11:18:56 UTC 2021 Modified Files: src/sys/dev/pci: pcidevs.h pcidevs_data.h Log Message: Regen. To generate a diff of this commit: cvs rdiff -u -r1.1425 -r1.1426 src/sys/dev/pci/pcidevs.h cvs rdiff -u -r1.1424

CVS commit: src/sys/dev/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 11:18:56 UTC 2021 Modified Files: src/sys/dev/pci: pcidevs.h pcidevs_data.h Log Message: Regen. To generate a diff of this commit: cvs rdiff -u -r1.1425 -r1.1426 src/sys/dev/pci/pcidevs.h cvs rdiff -u -r1.1424

CVS commit: src/sys/dev/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 11:18:23 UTC 2021 Modified Files: src/sys/dev/pci: pcidevs Log Message: Add Intel Gemini Lake TXE HECI 1. To generate a diff of this commit: cvs rdiff -u -r1.1440 -r1.1441 src/sys/dev/pci/pcidevs Please note that

CVS commit: src/sys/dev/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 11:18:23 UTC 2021 Modified Files: src/sys/dev/pci: pcidevs Log Message: Add Intel Gemini Lake TXE HECI 1. To generate a diff of this commit: cvs rdiff -u -r1.1440 -r1.1441 src/sys/dev/pci/pcidevs Please note that

CVS commit: src/sys/uvm/pmap

2021-10-27 Thread Simon Burge
Module Name:src Committed By: simonb Date: Wed Oct 27 06:54:15 UTC 2021 Modified Files: src/sys/uvm/pmap: pmap_tlb.c Log Message: TAB police. To generate a diff of this commit: cvs rdiff -u -r1.48 -r1.49 src/sys/uvm/pmap/pmap_tlb.c Please note that diffs are not public

CVS commit: src/sys/uvm/pmap

2021-10-27 Thread Simon Burge
Module Name:src Committed By: simonb Date: Wed Oct 27 06:54:15 UTC 2021 Modified Files: src/sys/uvm/pmap: pmap_tlb.c Log Message: TAB police. To generate a diff of this commit: cvs rdiff -u -r1.48 -r1.49 src/sys/uvm/pmap/pmap_tlb.c Please note that diffs are not public

CVS commit: src/tests/usr.bin/pwhash

2021-10-27 Thread Nia Alarie
Module Name:src Committed By: nia Date: Wed Oct 27 06:50:02 UTC 2021 Modified Files: src/tests/usr.bin/pwhash: t_pwhash.sh Log Message: t_pwhash: Don't assume default cipher is SHA1. Add Argon2 tests. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2

CVS commit: src/tests/usr.bin/pwhash

2021-10-27 Thread Nia Alarie
Module Name:src Committed By: nia Date: Wed Oct 27 06:50:02 UTC 2021 Modified Files: src/tests/usr.bin/pwhash: t_pwhash.sh Log Message: t_pwhash: Don't assume default cipher is SHA1. Add Argon2 tests. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2