Module Name:src
Committed By: skrll
Date: Mon Dec 5 07:33:43 UTC 2022
Modified Files:
src/libexec/ld.elf_so/arch/riscv: rtld_start.S
Log Message:
Use the SZREG symbol instead of __SIZEOF_POINTER__ as its shorter. Assert
that they're the same just in case.
Sprinkle some
Module Name:src
Committed By: skrll
Date: Mon Dec 5 07:33:43 UTC 2022
Modified Files:
src/libexec/ld.elf_so/arch/riscv: rtld_start.S
Log Message:
Use the SZREG symbol instead of __SIZEOF_POINTER__ as its shorter. Assert
that they're the same just in case.
Sprinkle some
Module Name:src
Committed By: skrll
Date: Mon Dec 5 07:26:25 UTC 2022
Modified Files:
src/libexec/ld.elf_so/arch/riscv: mdreloc.c
Log Message:
RISC-V is RELA
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/libexec/ld.elf_so/arch/riscv/mdreloc.c
Please
Module Name:src
Committed By: skrll
Date: Mon Dec 5 07:26:25 UTC 2022
Modified Files:
src/libexec/ld.elf_so/arch/riscv: mdreloc.c
Log Message:
RISC-V is RELA
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/libexec/ld.elf_so/arch/riscv/mdreloc.c
Please
Module Name:src
Committed By: skrll
Date: Sat Dec 3 09:39:44 UTC 2022
Modified Files:
src/libexec/ld.elf_so/arch/riscv: mdreloc.c rtld_start.S
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6
Module Name:src
Committed By: skrll
Date: Sat Dec 3 09:39:44 UTC 2022
Modified Files:
src/libexec/ld.elf_so/arch/riscv: mdreloc.c rtld_start.S
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6
