Module Name:src
Committed By: riastradh
Date: Wed Aug 29 15:52:27 UTC 2018
Modified Files:
src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/instmem:
nouveau_nvkm_subdev_instmem_nv40.c
Log Message:
No, this cannot be bar 0 -- it is bar 2 or bar 3, as shown
Module Name:src
Committed By: riastradh
Date: Wed Aug 29 15:46:31 UTC 2018
Modified Files:
src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/instmem:
nouveau_nvkm_subdev_instmem_nv40.c
Log Message:
Let's try not to use uninitialized memory as a bus size, s
Module Name:src
Committed By: riastradh
Date: Mon Aug 27 14:18:18 UTC 2018
Modified Files:
src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/instmem:
nouveau_nvkm_subdev_instmem_nv50.c
Log Message:
Don't forget to add the base address.
To generate a diff
Module Name:src
Committed By: riastradh
Date: Mon Aug 27 07:36:37 UTC 2018
Modified Files:
src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/instmem:
nouveau_nvkm_subdev_instmem_gk20a.c
Log Message:
Rewrite DMA/IOMMU stuff using bus_dma for gk20a.
To gen
Module Name:src
Committed By: riastradh
Date: Mon Aug 27 06:36:48 UTC 2018
Modified Files:
src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/instmem:
nouveau_nvkm_subdev_instmem_nv50.c
Log Message:
endif not endf
To generate a diff of this commit:
cvs rd
