Module Name:src
Committed By: kamil
Date: Wed Jun 27 17:39:30 UTC 2018
Modified Files:
src/tests/bin/expr: t_expr.sh
Log Message:
Add 3 more expr(1) ATF tests detecting overflow
Verify 0 * INT.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/tests/bin/ex
Module Name:src
Committed By: kamil
Date: Wed Jun 27 17:14:47 UTC 2018
Modified Files:
src/tests/bin/expr: t_expr.sh
Log Message:
Add a couple of new ATF expr(1) tests
Some of the newly covered test-cases contained regressions.
All tests pass.
To generate a diff of thi
Module Name:src
Committed By: kamil
Date: Tue Jun 12 18:54:40 UTC 2018
Modified Files:
src/tests/bin/expr: t_expr.sh
Log Message:
Add 2 new expr(1) ATF tests
Assert that -9223372036854775808 % -1 and -9223372036854775808 / -1 return
message about overflow / underflow dete
Module Name:src
Committed By: jruoho
Date: Tue Mar 27 07:23:06 UTC 2012
Modified Files:
src/tests/bin/expr: t_expr.sh
Log Message:
Add a check for old PR bin/2486.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/tests/bin/expr/t_expr.sh
Please note that
Module Name:src
Committed By: jruoho
Date: Tue Mar 20 06:30:02 UTC 2012
Modified Files:
src/tests/bin/expr: t_expr.sh
Log Message:
Note PR bin/12838.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/tests/bin/expr/t_expr.sh
Please note that diffs are not