Sun4d interrupt handling?

2007-12-04 Thread Blue Swirl
Hi, I'm adding Sun4d support to Qemu and I was wondering if there are any docs for Sun4d, especially interrupt handling (SBI, BW, counters, SMP issues, boards). Any pointers? Looking at Linux sources, it seems that SBI handles SBus interrupts and then BW masks all interrupt sources. Is BW CPU spe

Re: More than 4G of memory on Sparc32?

2007-09-28 Thread Blue Swirl
On 9/26/07, David Miller <[EMAIL PROTECTED]> wrote: > From: "Blue Swirl" <[EMAIL PROTECTED]> > Date: Wed, 26 Sep 2007 22:21:42 +0300 > > > Will this ever be fixed? Anybody out there with a real machine and > > lots of memory? > > Since you

More than 4G of memory on Sparc32?

2007-09-26 Thread Blue Swirl
Hi, I've tried to add support to Qemu (and OpenBIOS) for more than 4G of memory for the Sparc32 target. But now it seems that Linux can't use this memory after all. The first show stopper is this code in arch/sparc/prom/memory.c: 111 /* Grrr, have to traverse the prom device tree

Re: Sun4c interrupt controller - Sun4d relevance

2007-08-12 Thread Blue Swirl
On 8/12/07, Chris Newport <[EMAIL PROTECTED]> wrote: > This is VERY interesting as it should be possible to fix Sun4d by finding > the differences between sun4d and sun4m in Solaris and covering those > points. > > This would almost certainly be easier than trying to fix the current > mess. Unfortu

Re: Sun4c interrupt controller, MMU, IOMMU?

2007-08-12 Thread Blue Swirl
On 8/12/07, Mark Fortescue <[EMAIL PROTECTED]> wrote: > The attached file is work in progress so it may not be 100% correct. You > will need a wide screen (150 columns) to view the file. Thanks! So basically the virtual to physical translation can be emulated by the following code: #include type

Re: Sun4c interrupt controller, MMU, IOMMU?

2007-08-12 Thread Blue Swirl
On 8/12/07, David Miller <[EMAIL PROTECTED]> wrote: > > Specifically, how are the interrupts routed, which interrupts (ZS, > > ESP, Lance, timers, floppy, cgthree) go through the interrupt > > controller? > > There is no interrupt controller, the individual devices and > SBUS slot interrupt sources

Sun4c interrupt controller, MMU, IOMMU?

2007-08-12 Thread Blue Swirl
Hi, I'm trying to add Sun4c (SS-2) support to Qemu. I'm using Linux source as the reference, but some things are not very clear. Specifically, how are the interrupts routed, which interrupts (ZS, ESP, Lance, timers, floppy, cgthree) go through the interrupt controller? How do the controller bits

Re: [ANNOUNCE] Aurora SPARC Linux Build 2.98 (Beta 1 for 3.0)

2007-04-14 Thread Blue Swirl
> I'm testing the Aurora CDROM on Qemu (current CVS version). The > install seems to run fine, but at start Qemu gives the following error > messages a few times: > scsi-disk: Inquiry buffer too small (4) > > Maybe this message is related to esp errors? I don't think so, my Ultra60 installed perf

Re: [ANNOUNCE] Aurora SPARC Linux Build 2.98 (Beta 1 for 3.0)

2007-04-14 Thread Blue Swirl
Hi, I'm testing the Aurora CDROM on Qemu (current CVS version). The install seems to run fine, but at start Qemu gives the following error messages a few times: scsi-disk: Inquiry buffer too small (4) Maybe this message is related to esp errors? - To unsubscribe from this list: send the line "un

Proll updates

2005-04-18 Thread Blue Swirl
Hi, This version adds support for ESP SCSI controller (not the real, but Qemu one), Type 5 keyboard, and some more escape codes. Now Qemu can boot from a CD and one can use keyboard to select SILO options in graphical mode. I've also merged a patch from Debian. _

Re: Proll updates

2005-03-07 Thread Blue Swirl
Where do they come from, I wonder? What part of your distro produces them? My RHL did not print any escape sequences for colored "[ok]" on serial console. Linux prints the escape sequences at boot when console=prom. Proll prints the text to graphical console (TCX, black text on white bg). Later, w

Proll updates

2005-03-06 Thread Blue Swirl
Hi, I've added basic VT100 escape sequence processing to Proll, so that the screen is not full of garbage at boot. The code is stolen from Linux itself. Could someone with a real Javastation try the updated version? _ Don't just sea

Re: Who restores %g6 for trap/irq handlers?

2005-02-22 Thread Blue Swirl
It branches to "trap_setup" which is what sets up %g6 via the LOAD_CURRENT() macro we discussed earlier. Thanks, I found the bug: PS flag was always equal to S, so %g6 was assumed OK. Now we reach the userland: RAMDISK: Loading 64KiB [1 disk] into ram disk... done. VFS: Mounted root (ext2 filesys

Re: Who restores %g6 for trap/irq handlers?

2005-02-21 Thread Blue Swirl
Hi, %g6 is loaded at "arch/sparc/kernel/etrap.S:trap_setup_from_user" by the "LOAD_CURRENT()" macro. Yes, I used that when patching. At context switch time, it is updated by the switch_to() macro. There has been no context switch yet. At bootup, the first cpu sets up it's %g6 in arch/sparc/kernel/h

Who restores %g6 for trap/irq handlers?

2005-02-20 Thread Blue Swirl
Hi, Qemu's Sparc32 system emulator is getting to the point where the first user space application almost executes. But there is some strangeness with kernel's use of %g6, it's used for example in do_sparc_fault, but nothing is restoring it before that, so there is a kernel zero page access as a