OK. I'll try that.
Thanks a lot for your valuable help.
On 8/16/07, jiaqi zhang <[EMAIL PROTECTED]> wrote:
> On 8/15/07, David Miller <[EMAIL PROTECTED]> wrote:
>
> >
> > Check the component list from the ALOM prompt.
> >
> Do you mean the "showcomponent" command? I ran it and got the information:
From: "jiaqi zhang" <[EMAIL PROTECTED]>
Date: Thu, 16 Aug 2007 15:42:58 +1200
> Seems not of too much help?
>
> What should I do then?
If you can't decode that table and see that the virtual
cpu IDs are the same as the physical cpu IDs, perhaps
you should take my second recommendation and build
On 8/15/07, David Miller <[EMAIL PROTECTED]> wrote:
>
> Check the component list from the ALOM prompt.
>
Do you mean the "showcomponent" command? I ran it and got the information:
sc> showcomponent
Keys:
MB/CMP0/P0
MB/CMP0/P1
MB/CMP0/P2
MB/CMP0/P3
MB/CMP0/P4
MB/CMP0/P5
MB/CMP0/P6
M
From: "jiaqi zhang" <[EMAIL PROTECTED]>
Date: Wed, 15 Aug 2007 08:38:53 +1200
> I've checked the ALOM manual and found no useful clues there. If ALOM
> knows it, can I simply get the information from ALOM? Or should I have
> to ask hypervisor directly?
Check the component list from the ALOM promp
I've checked the ALOM manual and found no useful clues there. If ALOM
knows it, can I simply get the information from ALOM? Or should I have
to ask hypervisor directly?
Since my kernel is 2.6.20, which does not support your multi-core
arrangement for sparc64 yet, it lacks the mdesc files.
Thanks!
> You can look at the files under /sys/devices/system/cpu/cpu${ID}/topology/
> to see this information.
However, I find "topology" an empty directory:(
> This datastructure is parsed and managed in arch/sparc64/kernel/mdesc.c,
> in particular you might find mdesc_fill_in_cpu_data() useful.
Howeve
Thanks for your concern.
We are doing experiments on how the cache influences the performance.
Since the 4 threads on each physical core share the same cache,
performance should be different depending on whether 4 threads are on
the same core or not. And we want to measure this difference in our
From: "jiaqi zhang" <[EMAIL PROTECTED]>
Date: Tue, 14 Aug 2007 09:34:26 +1200
> Since I have to do some more tests on the cache problem of UltraSPARC
> T1,
What is this "cache problem"?
> I have to know the exact physical cpu id of each strand. Could
> anyone give me some clues on how the physic
Hello, everyone.
Thanks again for the previous help on the faultive instruction
problem. That works perfect:)
Since I have to do some more tests on the cache problem of UltraSPARC
T1, I have to know the exact physical cpu id of each strand. Could
anyone give me some clues on how the physical cpu
