On Tue, Sep 7, 2010 at 7:29 PM, Mark Brown
wrote:
> Allow the use of the S3C64xx SPI controller with things like PMICs by
> moving the init up to subsys_initcall().
>
> Signed-off-by: Mark Brown
> ---
>
> Incidentally I don't seem to see anything in the current SPI tree for
> -next - should the t
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spi-
On Wed, Sep 8, 2010 at 12:37 AM, Mark Brown
wrote:
> For small transfers at high speeds the expected transfer time can easily
> be well under 1ms, causing the delay in wait_for_xfer() to be only the
> dead reckoning fudge factor of 5ms currently included. Experiments on
> some of my systems shows
On Wed, Sep 8, 2010 at 12:37 AM, Mark Brown
wrote:
> In wait_for_xfer() for PIO transfer we are using val as both a
> counter variable to track the number of spins we've waited for
> completion and the value we read from the controller, causing
> us to fail to ever actually notice the timeout. Fix
For small transfers at high speeds the expected transfer time can easily
be well under 1ms, causing the delay in wait_for_xfer() to be only the
dead reckoning fudge factor of 5ms currently included. Experiments on
some of my systems shows that this is marginal for some transfers so
double it to 10m
In wait_for_xfer() for PIO transfer we are using val as both a
counter variable to track the number of spins we've waited for
completion and the value we read from the controller, causing
us to fail to ever actually notice the timeout. Fix this by using
a separate value to hold the register readbac
Allow the use of the S3C64xx SPI controller with things like PMICs by
moving the init up to subsys_initcall().
Signed-off-by: Mark Brown
---
Incidentally I don't seem to see anything in the current SPI tree for
-next - should the tree being used be updated or something?
drivers/spi/spi_s3c64xx
Allow interrupt sharing since exclusive interrupt line for
DW SPI controller is not provided on every platform.
Signed-off-by: Yong Wang
---
drivers/spi/dw_spi.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/dw_spi.c b/drivers/spi/dw_spi.c
index d256c
commit 052dc7c45i "spi/dw_spi: conditional transfer mode change"
introduced cs_control code, which has a bug by using bit offset
for spi mode to set transfer mode in control register. Also it
forces devices who don't need cs_control to re-configure the
control registers for each spi transfer. This
