On Mon, Sep 06, 2010 at 08:09:35PM +0900, Masayuki Ohtak wrote:
> SPI driver of Topcliff PCH
>
> Topcliff PCH is the platform controller hub that is going to be used in
> Intel's upcoming general embedded platform. All IO peripherals in
> Topcliff PCH are actually devices sitting on AMBA bus.
> T
Hello all,
I'm working 9 years as a Linux C/C++ programmer but I spent 99,9% of this
time working in user space programming, now I need to write a driver to use
the ADS1256 Analog-Digital converter (
http://focus.ti.com/docs/prod/folders/print/ads1256.html ) in an ARM board
using S3C2440 processor,
We can't do without setting channel and bus width to
same size. Inorder to do that, use loop read/writes in
polling mode and appropriate burst size in DMA mode.
Signed-off-by: Jassi Brar
---
drivers/spi/spi_s3c64xx.c | 56 +
1 files changed, 41 inser
On Fri, Sep 10, 2010 at 12:07:50AM +0900, Jassi Brar wrote:
> On Thu, Sep 9, 2010 at 11:51 PM, Grant Likely
> wrote:
> > On Thu, Sep 09, 2010 at 04:18:57PM +0900, Jassi Brar wrote:
[...]
> > Nit: switch statements like this tend to obscure the fact that the same
> > function is called each time w
On Thu, Sep 9, 2010 at 11:51 PM, Grant Likely wrote:
> On Thu, Sep 09, 2010 at 04:18:57PM +0900, Jassi Brar wrote:
>> We can't do without setting channel and bus width to
>> same size. Inorder to do that, use loop read/writes in
>> polling mode and appropriate burst size in DMA mode.
>>
>> Signed-
On Thu, Sep 09, 2010 at 04:19:04PM +0900, Jassi Brar wrote:
> Newer SoCs have the SPI clock scaling control in platform's
> clock management unit. Inorder for such SoCs to work, we need
> to check the flag clk_from_cmu before making any clock changes.
>
> Signed-off-by: Jassi Brar
Thanks, applie
On Thu, Sep 09, 2010 at 04:18:57PM +0900, Jassi Brar wrote:
> We can't do without setting channel and bus width to
> same size. Inorder to do that, use loop read/writes in
> polling mode and appropriate burst size in DMA mode.
>
> Signed-off-by: Jassi Brar
Looks pretty good to me. A couple of m
2010/9/9 Kevin Wells :
> Yes - the clients and the client setup info need some changes.
> I'm currently testing these patches and will post them soon.
OK great, can you make this a patch series?
Like
1/2 - changes to amba-pl022.c
2/2 - changes to clients
or so?
Yours,
Linus Walleij
--
2010/9/9 Grant Likely :
> Note on the subject line: The preferred form for spi patches is:
>
> spi[/chip]:
Ah OK I'll use that syntax henceforth. Thanks!
Linus Walleij
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Newer SoCs have the SPI clock scaling control in platform's
clock management unit. Inorder for such SoCs to work, we need
to check the flag clk_from_cmu before making any clock changes.
Signed-off-by: Jassi Brar
---
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |3 +
drivers/spi/spi_s3c64
We can't do without setting channel and bus width to
same size. Inorder to do that, use loop read/writes in
polling mode and appropriate burst size in DMA mode.
Signed-off-by: Jassi Brar
---
drivers/spi/spi_s3c64xx.c | 76 -
1 files changed, 61 inser
On Thu, Sep 9, 2010 at 2:07 PM, Grant Likely wrote:
> On Fri, Sep 03, 2010 at 10:36:54AM +0900, Jassi Brar wrote:
>> We can't do without setting channel and bus width to
>> same size.
>> Inorder to do that, define a new callback to be used
>> to do read/write of appropriate widths.
>>
>> Signed-of
On Thu, Sep 9, 2010 at 2:55 PM, Grant Likely wrote:
> On Thu, Sep 09, 2010 at 02:29:22PM +0900, Jassi Brar wrote:
>> On Thu, Sep 9, 2010 at 2:11 PM, Grant Likely
>> wrote:
>> > On Fri, Sep 03, 2010 at 10:37:10AM +0900, Jassi Brar wrote:
>> >> Newer SoCs have the SPI clock scaling control in plat
Hi Grant,
On Wed, Sep 08, 2010 at 11:33:16PM -0600, Grant Likely wrote:
> A description of what is required to add imx51 support would be
> appreciated by us poor patch reviewers.
Currently there are two different patches for adding imx51 support, one
by Sascha (sent by me) and one by Jason Wang.
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