Re: [PATCH] spi:add support for slave function in current spi framework

Hi Grant, Just come back from the long holiday. Thanks very much for the comment and hints. Following your idea here is some update of our plan: Yes the slave can not predict when the transaction is going to happen, and it takes time before the slave is ready for the transaction after the system

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Re: [PATCH v6 0/6] OMAP: McSPI: Hwmod adaptation + runtime conversion

* Kevin Hilman [110204 14:27]: > "Govindraj.R" writes: > > > Changes invloves: > > > > 1) Addition of hwmod data for omap2/3/4. > > 2) McSPI driver hwmod adaptation with cleanup of base address > >macros and using omap-device API's. > > 3) Runtime Conversion of McSPI driver.

[PATCH 8/8] intel_mid_ssp_spi: Implement slave side quirk

From: Alan Cox Signed-off-by: Alan Cox --- drivers/spi/intel_mid_ssp_spi.c | 32 +--- 1 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c index 8d7a157..91976af 100644 --- a/drivers/sp

[PATCH 7/8] intel_mid_ssp_spi: Bounce data through the Langwell SRAM when needed

From: Alan Cox This is required for Moorestown slave mode operation Based on earlier generic driver work by Mathieu SOULARD Signed-off-by: Alan Cox --- drivers/spi/intel_mid_ssp_spi.c | 123 ++- drivers/spi/intel_mid_ssp_spi_def.h |7 ++ 2 files chan

[PATCH 6/8] intel_mid_ssp_spi: Add the QoS quirk for slave mode

From: Alan Cox This is needed for Moorestown. Again we add this so that the default is off and the code changed is all within if (quirks & ). Baed on previous generic driver work by Mathieu SOULARD Signed-off-by: Alan Cox --- drivers/spi/intel_mid_ssp_spi.c | 16 1 files

[PATCH 5/8] intel_mid_ssp_spi: Add chip definitions

From: Alan Cox The quirk tweaks so far are sufficient for us to support master mode on all the devices. Put the PCI identifiers back. If they are in use for other things the vendor bits will ensure the driver doesn't claim the wrong ones. Add the missing MODULE tag so we can do autoloading Base

[PATCH 4/8] intel_mid_ssp_spi: Add the uglies needed for Moorestown master mode

From: Alan Cox We need to support the bitbanging quirk - triggered only on Moorestown so should have no impact on any Medfield code paths, and not poke around syscfg which is for Medfield, so if the Moorestown quirk is set skip that. Also fix a leak of syscfg in the Medfield path Merged from ea

[PATCH 3/8] intel_mid_ssp_spi: Implement the MRST quirk

From: Alan Cox This quirk simply changes the ID we use to find the DMA controller. Rename the define and select a different ID IFF the MRST quirk is set Signed-off-by: Alan Cox --- drivers/spi/intel_mid_ssp_spi.c | 12 1 files changed, 8 insertions(+), 4 deletions(-) diff --g

[PATCH 2/8] intel_mid_ssp_spi: Re-introduce quirks fields

From: Alan Cox This adds the quirks field to the driver and the flags. We don't yet implement any of them so we don't confuse the driver. Signed-off-by: Alan Cox --- drivers/spi/intel_mid_ssp_spi.c | 11 ++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/drivers/sp

[PATCH 1/8] Intel SPI master controller driver for the Medfield platform

From: Russ Gorby SPI master controller driver for the Intel MID platform Medfield This driver uses the Penwell SSP controller and configures it to be a SPI device (spibus 3). This bus supports a single device - the 3G SPI modem that can operate up to 25Mhz. Signed-off-by: Russ Gorby Signed-off-

[PATCH 0/8] Intel MID SSP SPI merged driver

This series of patches begins with Russ Gorby's posted driver for the Medfield platform with the SSP providing clock and adds back support for Moorestown in the form of additional quirks, as well as basic support for clock slave. This allows the kernel to have one driver which can drive all the SS