Add missing register bits and registers into mxs-spi.h .
These will be used by the SPI driver.
Based on previous attempt by:
Fabio Estevam
Signed-off-by: Fabio Estevam
Signed-off-by: Marek Vasut
Cc: Chris Ball
Cc: Detlev Zundel
CC: Dong Aisheng
Cc: Grant Likely
Cc: Linux ARM kernel
Cc: Ro
Abstract out the common part of private data shared between MMC
and SPI. These shall later allow to use common clock configuration
function.
Signed-off-by: Marek Vasut
Cc: Chris Ball
Cc: Detlev Zundel
CC: Dong Aisheng
Cc: Fabio Estevam
Cc: Grant Likely
Cc: Linux ARM kernel
Cc: Rob Herring
Signed-off-by: Marek Vasut
Cc: Chris Ball
Cc: Detlev Zundel
CC: Dong Aisheng
Cc: Fabio Estevam
Cc: Grant Likely
Cc: Linux ARM kernel
Cc: Rob Herring
CC: Shawn Guo
Cc: Stefano Babic
Cc: Wolfgang Denk
---
arch/arm/boot/dts/imx28.dtsi | 39 +++
1 file
These parts will be used by the MXS SPI driver too.
Signed-off-by: Marek Vasut
Cc: Chris Ball
Cc: Detlev Zundel
CC: Dong Aisheng
Cc: Fabio Estevam
Cc: Grant Likely
Cc: Linux ARM kernel
Cc: Rob Herring
CC: Shawn Guo
Cc: Stefano Babic
Cc: Wolfgang Denk
---
drivers/mmc/host/mxs-mmc.c |
Signed-off-by: Marek Vasut
Cc: Chris Ball
Cc: Detlev Zundel
CC: Dong Aisheng
Cc: Fabio Estevam
Cc: Grant Likely
Cc: Linux ARM kernel
Cc: Rob Herring
CC: Shawn Guo
Cc: Stefano Babic
Cc: Wolfgang Denk
---
Documentation/devicetree/bindings/spi/mxs-spi.txt | 18 ++
1 file
This is slightly reworked version of the SPI driver.
Support for DT has been added and it's been converted
to queued API.
Based on previous attempt by:
Fabio Estevam
Signed-off-by: Fabio Estevam
Signed-off-by: Marek Vasut
Cc: Chris Ball
Cc: Detlev Zundel
CC: Dong Aisheng
Cc: Grant Likely
C
Since the SSP controller can act as both SPI and MMC host,
renaming the enum to properly reflect the naming seems
appropriate.
Based on previous attempt by:
Fabio Estevam
Signed-off-by: Fabio Estevam
Signed-off-by: Marek Vasut
Cc: Chris Ball
Cc: Detlev Zundel
CC: Dong Aisheng
Cc: Grant Like
Signed-off-by: Marek Vasut
Cc: Chris Ball
Cc: Detlev Zundel
CC: Dong Aisheng
Cc: Fabio Estevam
Cc: Grant Likely
Cc: Linux ARM kernel
Cc: Rob Herring
CC: Shawn Guo
Cc: Stefano Babic
Cc: Wolfgang Denk
---
drivers/spi/spi-mxs.c | 230 +
1 fi
Pull out the MMC clock configuration function and make it
into SSP clock configuration function, so it can be used by
the SPI driver too.
Signed-off-by: Marek Vasut
Cc: Chris Ball
Cc: Detlev Zundel
CC: Dong Aisheng
Cc: Fabio Estevam
Cc: Grant Likely
Cc: Linux ARM kernel
Cc: Rob Herring
CC:
Move the definitions into separate file so separate SPI driver can be
implemented. The SSP controller in MXS can act both as a MMC host and
as a SPI host.
Based on previous attempt by:
Fabio Estevam
Signed-off-by: Fabio Estevam
Signed-off-by: Marek Vasut
Cc: Chris Ball
Cc: Detlev Zundel
CC:
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On 7/5/2012 4:54 AM, Arnd Bergmann wrote:
> On Thursday 05 July 2012, Sebastian Hesselbarth wrote:
>> Andrew,
>>
>> is it possible to group all gpio banks into one DT description?
>> For mach-dove it could be something like:
>>
>> gpio: gpio-controller {
>> compatible = "marvell, orion-gpi
Sebastian Hesselbarth writes:
> On 07/05/2012 04:54 PM, Arnd Bergmann wrote:
>> This way you have multiple nodes with the same register
>> and different names, which is not how it normally works.
>
> Ok.
>
>>> This would have the advantage that DT describes gpio-to-irq dependencies.
>>> Moreover,
> Something completely different I just noticed in the original patch:
>
> > @@ -90,6 +74,27 @@ static void pmu_irq_handler(unsigned int irq, struct
> > irq_desc *desc)
> > }
> > }
> >
> > +static int __initdata gpio0_irqs[4] = {
> > + IRQ_DOVE_GPIO_0_7,
> > + IRQ_DOVE_GPIO_8_15,
On 07/05/2012 04:54 PM, Arnd Bergmann wrote:
> This way you have multiple nodes with the same register
> and different names, which is not how it normally works.
Ok.
>> This would have the advantage that DT describes gpio-to-irq dependencies.
>> Moreover, nodes that reference gpios can do gpios =
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On Thursday 05 July 2012, Sebastian Hesselbarth wrote:
> Andrew,
>
> is it possible to group all gpio banks into one DT description?
> For mach-dove it could be something like:
>
> gpio: gpio-controller {
> compatible = "marvell, orion-gpio";
> ...
>
> bank0@d0400 {
>
On Thu, Jul 05, 2012 at 04:14:50PM +0200, Sebastian Hesselbarth wrote:
> On 07/05/2012 03:08 PM, Andrew Lunn wrote:
> >The issue is knowing what IRQ number to use for the secondary
> >interrupts.
> >
> >Orion use generic chip interrupts, both for the main interrupts and
> >the GPIO interrupts. This
Hi Wolfram,
since I guess you're gonna harvest SPI patches for the next merge window
could you please pull this set of PL022 patches?
The following changes since commit 6887a4131da3adaab011613776d865f4bcfb5678:
Linux 3.5-rc5 (2012-06-30 16:08:57 -0700)
are available in the git repository at:
On 07/05/2012 03:08 PM, Andrew Lunn wrote:
> The issue is knowing what IRQ number to use for the secondary
> interrupts.
>
> Orion use generic chip interrupts, both for the main interrupts and
> the GPIO interrupts. This does not yet support irq domain, so i have
> to layer a legacy domain on top.
On Thursday 05 July 2012, Andrew Lunn wrote:
> >
> > I'm wondering about this one. The other platforms usually put the secondary
> > interrupt controllers into the same match table, while you call
> > orion_gpio_of_init
> > from orion_add_irq_domain. Can you explain why you do this? Does it hav
Le Thu, 5 Jul 2012 15:15:22 +0200,
Andrew Lunn a écrit :
> > > The biggest problem i had, is the interaction between generic chip
> > > interrupts and irqdomain. There has been work to integrate the two,
> > > but its stalled. Either the work needs restarting and completing, or
> > > you need to
On Thu, Jul 05, 2012 at 02:58:01PM +0200, Thomas Petazzoni wrote:
> Hello,
>
> Le Thu, 5 Jul 2012 11:48:24 +0200,
> Andrew Lunn a ??crit :
>
> > The biggest problem i had, is the interaction between generic chip
> > interrupts and irqdomain. There has been work to integrate the two,
> > but its
> > +Required properties
> > +- compatible : Should be "marvell,orion-intc".
> > +- #interrupt-cells: Specifies the number of cells needed to encode an
> > + interrupt source. Supported value is <1>.
> > +- interrupt-controller : Declare this node to be an interrupt controller.
> > +- reg : Inter
Hello,
Le Thu, 5 Jul 2012 11:48:24 +0200,
Andrew Lunn a écrit :
> The biggest problem i had, is the interaction between generic chip
> interrupts and irqdomain. There has been work to integrate the two,
> but its stalled. Either the work needs restarting and completing, or
> you need to throw aw
Hi,
On 07/05/2012 02:33 PM, Mark Brown wrote:
> Saves some error handling and a small amount of code.
>
> Signed-off-by: Mark Brown
> Acked-by: Linus Walleij
Reviewed-by: Sylwester Nawrocki
--
Regards,
Sylwester
--
Saves some error handling and a small amount of code.
Signed-off-by: Mark Brown
Acked-by: Linus Walleij
---
drivers/spi/spi-s3c64xx.c | 19 +--
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index f4e2341..f6
On Tuesday 03 July 2012, Andrew Lunn wrote:
> Both IRQ and GPIO controllers can now be represented in DT. The IRQ
> controllers are setup first, and then the GPIO controllers. Interrupts
> for GPIO lines are placed directly after the main interrupts in the
> interrupt space.
Overall looks very go
On 07/05/2012 01:48 PM, Andrew Lunn wrote:
>> Yes. I am not sure yet how to describe those in the DT, or even if it
>> is actually useful to describe them. Wouldn't it be simpler to just
>> leave to the user of the GPIO to use a GPIO that's appropriate for its
>> usage, i.e not use a GPO when i
Hi Thomas
> Yes. I am not sure yet how to describe those in the DT, or even if it
> is actually useful to describe them. Wouldn't it be simpler to just
> leave to the user of the GPIO to use a GPIO that's appropriate for its
> usage, i.e not use a GPO when input is needed?
We assume the hardware
Le Thu, 05 Jul 2012 12:38:51 +0200,
Arnaud Patard (Rtp) a écrit :
> > The MPP registers are identical on Armada XP/370 and 88F6281 (not sure
> > which other SoC datasheet I should be checking). Basically, it's just a
> > range of contiguous registers, with 4 bits per pin to select the
> > functio
Thomas Petazzoni writes:
> Le Thu, 05 Jul 2012 12:11:40 +0200,
> Arnaud Patard (Rtp) a écrit :
>
>> > You are not the only one working in this area. Arnaud Patard said he
>> > was look at this as well.
>>
>> yeah, but tbh I've not made anything yet. If Thomas has already some
>> code for it, w
Andrew Lunn writes:
Hi,
> On Thu, Jul 05, 2012 at 11:02:51AM +0200, Thomas Petazzoni wrote:
>> Hello Andrew,
>>
>> Le Tue, 3 Jul 2012 16:22:34 +0200,
>> Andrew Lunn a ??crit :
>>
>> > Both IRQ and GPIO controllers can now be represented in DT. The IRQ
>> > controllers are setup first, and t
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> I've looked at the datasheet for the 88F6281, and the GPIO registers
> look fairly similar with Armada 370/XP, except that:
>
> * On 88F6281, there are two GPIO banks, while on Armada 370/XP it's a
>continuous range of registers that control the GPIOs. But it can be
>assimilated as one
Le Thu, 05 Jul 2012 12:11:40 +0200,
Arnaud Patard (Rtp) a écrit :
> > You are not the only one working in this area. Arnaud Patard said he
> > was look at this as well.
>
> yeah, but tbh I've not made anything yet. If Thomas has already some
> code for it, we should try to make it "generic" so
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Hello,
Le Thu, 5 Jul 2012 11:48:24 +0200,
Andrew Lunn a écrit :
> Hi Thomas
>
> You are not the only one working in this area. Arnaud Patard said he
> was look at this as well.
Ok, I added Arnaud in the Cc list. Arnaud, what is the status of you
work?
> > So far, the pin muxing part is worki
On Thu, Jul 05, 2012 at 11:02:51AM +0200, Thomas Petazzoni wrote:
> Hello Andrew,
>
> Le Tue, 3 Jul 2012 16:22:34 +0200,
> Andrew Lunn a ??crit :
>
> > Both IRQ and GPIO controllers can now be represented in DT. The IRQ
> > controllers are setup first, and then the GPIO controllers. Interrupts
On Thu, Jul 5, 2012 at 2:53 PM, Shubhrajyoti D wrote:
> The dma_map and dma_unmap should have same parameter
> passed otherwise we get the below warn.
>
> ks8851 spi1.0: DMA-API: device driver tries to free DMA memory it has not
> allocated [device address=0x9f22]
>
> [2.066925] Modul
The dma_map and dma_unmap should have same parameter
passed otherwise we get the below warn.
ks8851 spi1.0: DMA-API: device driver tries to free DMA memory it has not
allocated [device address=0x9f22]
[2.066925] Modules linked in:
[2.070312]
[2.071929] [] (unwind_backtrace+0x
Hello Andrew,
Le Tue, 3 Jul 2012 16:22:34 +0200,
Andrew Lunn a écrit :
> Both IRQ and GPIO controllers can now be represented in DT. The IRQ
> controllers are setup first, and then the GPIO controllers. Interrupts
> for GPIO lines are placed directly after the main interrupts in the
> interrup
On 07/04/2012 06:11 PM, Mark Brown wrote:
> Saves some error handling and a small amount of code.
>
> Signed-off-by: Mark Brown
> Acked-by: Linus Walleij
> ---
> drivers/spi/spi-s3c64xx.c | 25 +
> 1 file changed, 1 insertion(+), 24 deletions(-)
>
> diff --git a/drive
On Thu, Feb 09, 2012 at 10:21:45PM +0100, Uwe Kleine-König wrote:
> The chip select line was configured as output with the initial value
> being active explicitly. It was later deasserted during
> spi_bitbang_setup() without any clock activity in between. So it makes
> no sense to activate the devi
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