From: Jason Cooper [mailto:ja...@lakedaemon.net]
Sent: Tuesday, February 05, 2013 8:09 PM
On Tue, Feb 05, 2013 at 06:07:05PM +0100, Thomas Petazzoni wrote:
Of course, it doesn't make sense to have drivers for pluggable devices
like PCIe devices that are not soldered, USB devices and
On Tuesday 05 February 2013 at 15:29:09, Grant Likely wrote:
On Thu, 31 Jan 2013 21:51:36 +0100, Linus Walleij
linus.wall...@linaro.org wrote:
On Thu, Jan 31, 2013 at 4:58 PM, Lars Poeschel la...@wh2.tu-dresden.de
wrote:
--- /dev/null
+++
On Tue, Feb 5, 2013 at 6:32 PM, Grant Likely grant.lik...@secretlab.ca wrote:
On Fri, 18 Jan 2013 10:03:28 +0100, Thomas De Schampheleire
patrickdepinguin+spide...@gmail.com wrote:
Hi,
The Freescale eSPI controller driver is broken in several ways. I already
attempted to fix this with a
On Wed, Feb 6, 2013 at 10:31 AM, Lars Poeschel poesc...@lemonage.de wrote:
The thing that confused me was, that the platform_data for the chip has a
mandatory base member, that sets the linux global gpio number at which the
chip should appear.
Yes this is common. I think you should look at
On Tue, 5 Feb 2013 15:09:41 -0800, Girish K S girishks2...@gmail.com wrote:
The status of the interrupt is available in the status register,
so reading the clear pending register and writing back the same
value will not actually clear the pending interrupts. This patch
modifies the interrupt
On 02/06/2013 02:06 PM, Ezequiel Garcia wrote:
This is second version of the SPI patchset for Armada 370/XP.
This series first adds support for the SPI controller
and then adds the SPI flash for the Armada XP GP board.
This series is based on 3.8-rc5 plus:
* arm: mvebu: support for the
On Wed, Feb 06, 2013 at 02:16:54PM +0100, Gregory CLEMENT wrote:
On 02/06/2013 02:06 PM, Ezequiel Garcia wrote:
This is second version of the SPI patchset for Armada 370/XP.
This series first adds support for the SPI controller
and then adds the SPI flash for the Armada XP GP board.
(Adding mtd in Cc)
On Wed, Feb 06, 2013 at 07:54:31AM -0300, Ezequiel Garcia wrote:
Hi Gregory,
On Tue, Feb 05, 2013 at 09:17:02PM +0100, Gregory CLEMENT wrote:
On 02/05/2013 05:28 PM, Gregory CLEMENT wrote:
Hi Ezequiel,
On 02/05/2013 12:24 PM, Ezequiel Garcia wrote:
This patch
From: Lars Poeschel poesc...@lemonage.de
I wanted to use mcp23s08 driver with a device that boots using device tree.
I modified the driver to allow the DT usage and tested with a mcp23017
which is a i2c device. I could not test the spi path, because I have no
such device.
Regards,
Lars
Lars
From: Lars Poeschel poesc...@lemonage.de
This converts the mcp23s08 driver to be able to be used with device
tree.
There is a special mcp,chips property, that correspond to the chips
member of the struct mcp23s08_platform_data. It can be used for
multiple mcp23s08/mc23s17 on the same spi
From: Lars Poeschel poesc...@lemonage.de
Explicitly allow -1 as a legal value for the
mcp23s08_platform_data-base. This is the special value lets the
kernel choose a valid global gpio base number.
Signed-off-by: Lars Poeschel poesc...@lemonage.de
---
drivers/gpio/gpio-mcp23s08.c |4 ++--
1
On 02/05/2013 02:07 PM, Grant Likely wrote:
On Sun, 27 Jan 2013 03:33:59 +, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
On Wed, Jan 09, 2013 at 06:31:09PM +0100, Lars-Peter Clausen wrote:
The second function spi_sync_transfer() takes a SPI device and an array of
spi_transfers.
On Wed, Feb 6, 2013 at 2:26 AM, Grant Likely grant.lik...@secretlab.ca wrote:
On Tue, 5 Feb 2013 15:09:41 -0800, Girish K S girishks2...@gmail.com wrote:
The status of the interrupt is available in the status register,
so reading the clear pending register and writing back the same
value will
On Wed, Feb 6, 2013 at 2:35 AM, Grant Likely grant.lik...@secretlab.ca wrote:
On Tue, 5 Feb 2013 15:09:42 -0800, Girish K S girishks2...@gmail.com wrote:
The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.
On Wed, Feb 6, 2013 at 2:40 AM, Grant Likely grant.lik...@secretlab.ca wrote:
On Tue, 5 Feb 2013 15:09:43 -0800, Girish K S girishks2...@gmail.com wrote:
This patch adds support for spi controllers with
dedicated clk/miso/mosi/cs pins. It skips the gpio
parsing and initialization for
On Wed, Feb 6, 2013 at 8:12 PM, Girish KS girishks2...@gmail.com wrote:
On Wed, Feb 6, 2013 at 2:26 AM, Grant Likely grant.lik...@secretlab.ca
wrote:
On Tue, 5 Feb 2013 15:09:41 -0800, Girish K S girishks2...@gmail.com
wrote:
The status of the interrupt is available in the status register,
On Wed, Feb 6, 2013 at 3:48 PM, Grant Likely grant.lik...@secretlab.ca wrote:
On Wed, Feb 6, 2013 at 8:12 PM, Girish KS girishks2...@gmail.com wrote:
On Wed, Feb 6, 2013 at 2:26 AM, Grant Likely grant.lik...@secretlab.ca
wrote:
On Tue, 5 Feb 2013 15:09:41 -0800, Girish K S
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