#x27;t cost too much as mentioned by Andrew
>
> First of all I think that the cost of re-awakening an already running
> thread is lower than the logic of testing bits. My note was just
> nit-picking: there is a window between when the task was woken-up and
&g
Am Donnerstag, den 04.03.2010, 15:25 +0800 schrieb Feng Tang:
> Hi All,
>
> Here is a driver for Maxim 3110 SPI-UART device, please help to review.
>
> It has been validated with Designware SPI controller (drivers/spi: dw_spi.c &
> dw_spi_pci.c). It supports polling and IRQ mode, supports batch r
Am Mittwoch, den 30.12.2009, 00:05 +0800 schrieb Tang, Feng:
> >-Original Message-
> >From: Baruch Siach [mailto:bar...@tkos.co.il]
> >Sent: 2009年12月29日 23:00
> >To: Tang, Feng
> >Cc: Greg Kroah-Hartman; David Brownell; Grant Likely; spi-devel-list;
> >linux-ser...@vger.kernel.org; a...@lxo
Am Donnerstag, den 21.08.2008, 11:47 +0200 schrieb Hendrik Sattler:
> Zitat von Erwin Authried <[EMAIL PROTECTED]>:
>
> > Am Donnerstag, den 21.08.2008, 10:46 +0200 schrieb Hendrik Sattler:
> >> Hi,
> >>
> >> I contact you because you are mentioned in
Am Donnerstag, den 21.08.2008, 10:46 +0200 schrieb Hendrik Sattler:
> Hi,
>
> I contact you because you are mentioned in the MAINTAINERS file of
> linux-2.6.26 for the mmc_spi drive and SPI subsystem.
>
> I want to share the bus with other SPI devices. The drivers mentions
> pending updates t
I'm I'm using something close to your description. On the SPI master, I
have one chipselect (SS)only. When the master starts a transfer to SPI
device N, it activates SS and sends the slave address as the first byte.
When the SPI bridge receives the address byte, it activates the
chipselect for the
when cs_change is set on the last part of the spi transfer, the
chipselect is kept active after the transfer as expected. When a new
transfer is started with a different chipselect, the first chipselect
isn't deselected. Shouldn't the driver make sure that there is never
more than one chipselect ac
