Hi Mark,
2013/6/3 Mark Brown broo...@sirena.org.uk:
On Mon, Jun 03, 2013 at 05:43:34PM -0400, Scott Jiang wrote:
+#define START_STATE ((void *)0)
+#define RUNNING_STATE((void *)1)
+#define DONE_STATE ((void *)2)
+#define ERROR_STATE ((void *)-1)
This looks icky due to the
New spi controller is integrated into Blackfin 6xx processor.
Comparing to bf5xx spi controller, we support 32 bits word size
and independent receive and transmit DMA channels now.
Also mode 0 and 2 (CPHA = 0) can get fully supported
becasue cs line may be controlled by the software.
On Tue, Jun 4, 2013 at 3:13 AM, Scott Jiang scott.jiang.li...@gmail.com wrote:
diff --git a/drivers/spi/spi-bfin6xx.c b/drivers/spi/spi-bfin6xx.c
+#include linux/workqueue.h
Why do you need this?
--
Get 100%
2013/6/3 Viresh Kumar viresh.ku...@linaro.org:
On Tue, Jun 4, 2013 at 3:13 AM, Scott Jiang scott.jiang.li...@gmail.com
wrote:
diff --git a/drivers/spi/spi-bfin6xx.c b/drivers/spi/spi-bfin6xx.c
+#include linux/workqueue.h
Why do you need this?
Sorry, I forgot to remove this line when I
New spi controller is integrated into Blackfin 6xx processor.
Comparing to bf5xx spi controller, we support 32 bits word size
and independent receive and transmit DMA channels now.
Also mode 0 and 2 (CPHA = 0) can get fully supported
becasue cs line may be controlled by the software.
---
Hi Scott,
Some minor comments?
On Tue, Jun 5, 2012 at 12:51 AM, Scott Jiang
scott.jiang.li...@gmail.com wrote:
New spi controller is integrated into Blackfin 6xx processor.
Comparing to bf5xx spi controller, we support 32 bits word size
and independent receive and transmit DMA channels now.
