Re: [PATCH V2 05/12] spi/mxs: Fix chip select control bits in DMA mode

Dear Trent Piepho, > In DMA mode the chip select control bits would be ORed into the CTRL0 > register without first clearing the bits. This means that after > addressing slave 1 the bit would be still be set when addressing slave > 0, resulting in slave 1 continuing to be addressed. > > The mess

[PATCH V2 05/12] spi/mxs: Fix chip select control bits in DMA mode

In DMA mode the chip select control bits would be ORed into the CTRL0 register without first clearing the bits. This means that after addressing slave 1 the bit would be still be set when addressing slave 0, resulting in slave 1 continuing to be addressed. The message handing function would pass