On 05/13/2011 12:24 PM, Linus Walleij wrote:
> 2011/5/13 viresh kumar :
>> Linus, Jamie,
>>
>> Have you ever seen this kind of issue? Which spi slave memories did you used
>> for testing?
>> I am using standard pl0022 and m25p80 driver. Tried in all modes: polling,
>> interrupt, dma.
>
> Not rea
On Fri, May 13, 2011 at 09:22:57AM +0530, viresh kumar wrote:
> On 05/11/2011 09:37 AM, viresh kumar wrote:
> > Actually i am seeing a different behavior by some of the spi
> > memories, like m25p10.
> > If there is a delay between read_sts_reg command and dummy bytes, then
> > 0xFF is
> > re
2011/5/13 viresh kumar :
> On 05/11/2011 09:37 AM, viresh kumar wrote:
>>
>> Hello,
>>
>> Following is what i understood after reading m25p80 driver and spi master
>> drivers in drivers/spi folder.
>>
>> "chip_select signal controls start and end of transfer. For ex: if we have
>> to read
>> statu
On 05/11/2011 09:37 AM, viresh kumar wrote:
>
> Hello,
>
> Following is what i understood after reading m25p80 driver and spi master
> drivers in drivers/spi folder.
>
> "chip_select signal controls start and end of transfer. For ex: if we have to
> read
> status reg of spi memory, then we use
On Wed, May 11, 2011 at 09:37:19AM +0530, viresh kumar wrote:
> Following is what i understood after reading m25p80 driver and spi
> master drivers in drivers/spi folder.
>
> "chip_select signal controls start and end of transfer. For ex: if we have to
> read
> status reg of spi memory, then we
On 05/11/2011 12:47 PM, Jamie Iles wrote:
> What SPI controller are you using? I've seen a similar issue with the
> Synopsys DesignWare SPI controller where the controller manages the chip
> select itself, and once the FIFO is emptied the CS goes away, but the
> flash chip requires it to stay h
Hello,
Following is what i understood after reading m25p80 driver and spi master
drivers in drivers/spi folder.
"chip_select signal controls start and end of transfer. For ex: if we have to
read
status reg of spi memory, then we use write_and_then_read() routine. which
writes
0x9F in one spi t
