Original Message -
From: D. Richard Hipp [EMAIL PROTECTED]
To: sqlite-users@sqlite.org
Sent: Thursday, August 18, 2005 9:24 AM
Subject: Re: [sqlite] Possible bug regarding endiannes and real storageclass
(sqlite3)
On Thu, 2005-08-18 at 18:04 +0200, Frank van Vugt wrote:
L.S
On Thu, 2005-08-18 at 09:40 -0700, Robert Simpson wrote:
http://www.psc.edu/general/software/packages/ieee/ieee.html
The way I interpreted this site, is that the IEEE standard for floating
point numbers was processor agnostic and the storage of the bits went from
left to right.
I wrote
On Thu, 2005-08-18 at 14:10 -0400, D. Richard Hipp wrote:
On Thu, 2005-08-18 at 09:40 -0700, Robert Simpson wrote:
http://www.psc.edu/general/software/packages/ieee/ieee.html
The way I interpreted this site, is that the IEEE standard for floating
point numbers was processor agnostic and
Hi,
My test code is below. Please run this on your ARM and let
me know what you get.
# ./test
f03f
0100
It's getting smelly.. 32 bits only?
--
Best,
Frank.
See http://lists.debian.org/debian-arm/2003/10/msg00030.html
ARM has at least two FL formats.
from the ARM Architecture Reference Manual, Page C2-4:
The word order [for DP format] defined here for the VFP architecture
differs from that of the earlier FPA floating-point architecture. In
the
ARM has at least two FL formats.
Yes, I'm currently rebuilding my crosscompiler with specific soft-float
options, but it'll take a while.
Also, it seems that apart from the endiannes of the processor, there's also
'endiannes of peripheral wiring', i.e. the way the memory is connected to the
