From: Richard Weinberger rich...@nod.at
get_peb_for_wl() removes the PEB from the free list.
If the WL subsystem detects that no wear leveling is needed
it cancels the operation and drops the gained PEB.
In this case we have to put the PEB back into the free list.
This issue was introduced with
On Wed, Jan 30, 2013 at 02:16:00PM +0100, Steffen Trumtrar wrote:
The mxc-timer on the imx25 needs to be derived from the AHB clock.
If a bootloader reparents this clock to the ipg_clk_highfreq, which according
to the datasheet is a valid operation, the system can/will produce lockups/
freezes
On Fri, Nov 16, 2012 at 03:39:24PM +0100, Christoph Fritz wrote:
This patch sets HPM (Host power mask bit) to bit 16 according to i.MX
Reference Manual. Falsely it was set to bit 8, but this controls pull-up
Impedance.
Reported-by: Michael Burkey mdbur...@gmail.com
Cc: Stable
shawn@linaro.org
Acked-by: Sascha Hauer s.ha...@pengutronix.de
---
arch/arm/mach-imx/mach-mx51_babbage.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c
b/arch/arm/mach-imx/mach-mx51_babbage.c
index 7b31cbd..83f49c4
for the EIM interface?
It's not obvious from the datasheet and this information might help
people who want to clean up the now unconditionally enabled clocks.
Otherwise:
Acked-by: Sascha Hauer s.ha...@pengutronix.de
Sascha
Cc: stable@vger.kernel.org
Signed-off-by: Shawn Guo shawn@linaro.org
On Tue, Jun 26, 2012 at 05:26:16PM +0200, Sascha Hauer wrote:
The gpmi-nand driver uses virt_addr_valid() to check whether a buffer
is suitable for dma. If it's not, a driver allocated buffer is used
instead. Then after a page read the driver allocated buffer must be
copied to the user
Shijie b32...@freescale.com
Signed-off-by: Artem Bityutskiy artem.bityuts...@linux.intel.com
Signed-off-by: David Woodhouse david.woodho...@intel.com
This patch fixes this. The bug is encountered with UBI which uses a vmalloced
buffer for the volume table.
Signed-off-by: Sascha Hauer s.ha
MX53_DPLL4_BASE accidently returned the base address of PLL3.
Fix this.
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
Cc: stable@vger.kernel.org
---
arch/arm/mach-imx/crm-regs-imx5.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/crm-regs-imx5.h
b
nand_scan_tail checks for correct ecc strength
settings, so we must set them up before nand_scan_tail.
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
Cc: stable@vger.kernel.org
---
drivers/mtd/nand/mxc_nand.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
