he is to invalidate the entire instruction cache.
> + */
> if (l1ip != ICACHE_POLICY_PIPT)
> set_bit(ICACHEF_ALIASING, &__icache_flags);
> if (l1ip == ICACHE_POLICY_AIVIVT)
With the minor cosmetic changes:
Acked-by: Will Deacon
although I don't see how w
On Wed, Nov 04, 2015 at 09:22:13AM +0800, Boqun Feng wrote:
> Will, AFAIK, you are currently working on variants on arm64, right? I
> wonder whether you depend on patch 3 (allow archictures to provide
> self-defined __atomic_op_*), if so I can also send patch 3 as a patch
> for tip tree and wait un
to *data once we
know that the update has happened.
Cc: # 4.1, 4.2
Fixes: bd35a4adc413 ("arm64: Port SWP/SWPB emulation support from arm")
Reported-by: Shengjiu Wang
Reported-by: Vladimir Murzin
Signed-off-by: Will Deacon
---
arch/arm64/kernel/armv8_deprecated.c | 18 ++--
). This keeps
the reserved ASIDs in-sync with the mm and avoids the problem.
Cc:
Reported-by: Tony Thompson
Reviewed-by: Catalin Marinas
Signed-off-by: Will Deacon
---
arch/arm/mm/context.c | 39 ++-
1 file changed, 26 insertions(+), 13 deletions(-)
diff --git
). This keeps
the reserved ASIDs in-sync with the mm and avoids the problem.
Cc:
Reported-by: Tony Thompson
Reviewed-by: Catalin Marinas
Signed-off-by: Will Deacon
---
v1 -> v2: Don't remove clearing of mm_cpumask on rollover.
arch/arm/mm/context.c | 38
writing the TTBR.
Cc: # v3.14+, for older kernels need to drop the
'ishst'
Signed-off-by: Will Deacon
---
arch/arm64/mm/mmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index c04def90f3e4..c5bd5bca8e3d 100644
--- a/arch/arm64/mm/m
On Thu, Dec 10, 2015 at 06:14:12PM +, Mark Rutland wrote:
> Hi Will,
Hi Mark,
> On Thu, Dec 10, 2015 at 05:39:59PM +, Will Deacon wrote:
> > In paging_init, we allocate the zero page, memset it to zero and then
> > point TTBR0 to it in order to avoid speculative f
On Fri, Dec 11, 2015 at 06:19:52PM +, Mark Rutland wrote:
> > > > + /* Ensure the zero page is visible to the page table walker */
> > > > + dsb(ishst);
> > >
> > > I think this should live in early_alloc (likewise in late_alloc).
> > >
> > > In the other cases we call early_alloc
don't bother
to iterate over the ptes if we're at the final level.
Cc:
Reported-by: Zhang Bo
Signed-off-by: Will Deacon
---
drivers/iommu/io-pgtable-arm.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/i
the table construction into C).
This patch is intended for -stable trees based on v3.17 or v3.18.
Cc: # 3.17 and 3.18 only
Fixes: a97a42c47608 ("arm64: compat: wire up memfd_create and getrandom
syscalls for aarch32")
Reported-by: Edmund Grimley-Evans
Signed-off-by: Will Deacon
---
ar
On Thu, Apr 25, 2013 at 09:20:44AM +0100, Paul Bolle wrote:
> On Thu, 2013-04-25 at 17:02 +0900, Jonghwan Choi wrote:
> > This patch looks like it should be in the 3.8-stable tree, should we apply
> > it?
>
> That would be only the setup.c chunk. That fixes a typo introduced in
> v3.4 (see commit
On Sat, Mar 16, 2013 at 03:32:43AM +, chpoph wrote:
> On Sat, Mar 16, 2013 at 2:14 AM, Russell King - ARM Linux
> wrote:
> > We don't support different CPUs running at different frequencies with
> > the delay loop. Sorry.
>
> Does it means that a timer-based delay implementation must be used
(-1)/* from resource */
> -
> #elif defined(CONFIG_MN10300)
Ha! I was about to post a different fix for this issue, see below. I think
we may want a combination of the two...
Will
--->8
>From 2b4db3f7ddd560bc52be522098a96a6d18388f0f Mon Sep 17 00:00:00 2001
From: Will Deacon
D
-
> 1 file changed, 4 insertions(+), 18 deletions(-)
Acked-by: Will Deacon
Cheers for sorting that out, Linus.
Will
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until
probing has completed.
Cc:
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index c3642cc..2931921 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-s
Cc: Paolo Bonzini
Cc: Joel Schopp
Cc: Don Dutile
Cc: Peter Maydell
Cc:
Signed-off-by: Will Deacon
---
Paulo, Gleb,
This fixes a *really* nasty bug with 64k-page hosts and KVM. I believe
Marc and Christoffer are both on holiday at the moment (not together),
so could you please take this as an
On Thu, Jul 24, 2014 at 08:47:23PM +0100, Peter Maydell wrote:
> On 24 July 2014 20:27, Will Deacon wrote:
> > If the physical address of GICV isn't page-aligned, then we end up
> > creating a stage-2 mapping of the page containing it, which causes us to
> > map nei
Hi Peter,
On Thu, Jul 24, 2014 at 09:05:39PM +0100, Peter Maydell wrote:
> On 24 July 2014 20:55, Will Deacon wrote:
> > Again, that can be solved by introduced Marc's attr for determining the
> > GICV offset within the 64k page. I don't think that's -stable mater
Hi Joel,
On Fri, Jul 25, 2014 at 03:02:58PM +0100, Joel Schopp wrote:
> I can't think of any way of determining whether a particular
> system gets this right or wrong automatically, which suggests
> perhaps we need to allow the device tree to specify that the
> GICV is 64k-page
On Fri, Jul 25, 2014 at 03:16:15PM +0100, Joel Schopp wrote:
> On 07/25/2014 09:08 AM, Will Deacon wrote:
> >> This would break with my SOC device tree which looks like this. Note
> >> this device tree works just fine without checks.
> >>
> >>
el this will cause reading /proc/pid/pagemap of a
> 64-bit process from a 32-bit process to return EOF when it reads
> past 0x.
>
> Implement TASK_SIZE_OF exactly the same as TASK_SIZE with
> test_tsk_thread_flag instead of test_thread_flag.
Looks sane to me.
Acked-
On Wed, Jan 22, 2014 at 11:25:14AM +, Wang Nan wrote:
> This patch relaxes the restriction set by commit 309caa9cc, which
> prohibit ioremap() on all kernel managed pages.
>
> Other architectures, such as x86 and (some specific platforms of) powerpc,
> allow such mapping.
>
> ioremap() pages
r/o,
kernel r/w. All other user r/o pages are mapped also as kernel r/o.
Patch co-developed with Russell King.
Cc:
Signed-off-by: Will Deacon
---
arch/arm/include/asm/futex.h | 6 --
arch/arm/include/asm/pgtable-2level.h | 1 +
arch/arm/mm/Kconfig | 3 +--
arch
of the dsb()
macro and ensure ordering against the unlock.
Cc:
Reported-by: Mark Rutland
Signed-off-by: Will Deacon
---
arch/arm/include/asm/spinlock.h | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/
cached in the TLB.
This patch reworks the init functions so that the dsb used to ensure
completion of cache/predictor maintenance is also used to ensure
completion of the TLB invalidation.
Cc:
Reported-by: Albin Tonnerre
Signed-off-by: Will Deacon
---
arch/arm/mm/proc-v6.S | 3 ++-
arch/arm/mm
atch implements this solution for our barriered atomic operations,
ensuring that we satisfy the full barrier requirements where they are
needed.
Cc:
Cc: Catalin Marinas
Cc: Peter Zijlstra
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/atomic.h | 29 -
arch/a
Hi Peter,
On Tue, Feb 04, 2014 at 04:43:08PM +, Peter Zijlstra wrote:
> On Tue, Feb 04, 2014 at 12:29:12PM +0000, Will Deacon wrote:
> > @@ -112,17 +114,20 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int
> > old, int new)
> > unsigned long tm
with
GFP_ATOMIC instead of GFP_KERNEL.
Cc:
Reported-by: Andreas Herrmann
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 9f210de6537e..6eb5
s the problem by moving the pud/pmd population out of the
loop and instead performing it when we allocate the next level (like we
correctly do for ptes already). The starting address for the next level
is then calculated prior to entering the loop.
Cc:
Signed-off-by: Yifan Zhang
Signed-off-by:
NULL).
This patch fixes the code so that we remove the bp check and use the
correct index for accessing the watchpoint structures.
Cc:
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/hw_breakpoint.h | 1 -
arch/arm64/kernel/ptrace.c | 3 ++-
2 files changed, 2 insertions(
debug exceptions on the debug exception
return path when the exception was taken from EL1.
Cc:
Reported-by: David Long
Reported-by: AKASHI Takahiro
Signed-off-by: Will Deacon
---
arch/arm64/kernel/entry.S | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64
On Wed, Oct 08, 2014 at 04:06:12AM +0100, zhangzhiqiang wrote:
> hi all,
>
>
> ref-cycles event is specially to Intel core, but can still used in arm
> architecture
> with the wrong return value with 3.10 stable. for instance:
>
> perf stat -e ref-cycles
On Wed, Oct 08, 2014 at 02:31:47PM +0100, gre...@linuxfoundation.org wrote:
> On Wed, Oct 08, 2014 at 10:17:41AM +0100, Will Deacon wrote:
> > On Wed, Oct 08, 2014 at 04:06:12AM +0100, zhangzhiqiang wrote:
> > > hi all,
> > >
&g
used to check the data
first), we don't need to worry about calling __fls(0), which is
undefined.
Cc:
Cc: Victor Kamensky
Signed-off-by: Will Deacon
---
Hi Linus,
Victor reported this with a big-endian arm64 system. This is the
cleanest, most efficient solution I could come up with, but i
Hi Peter,
On Wed, Apr 30, 2014 at 10:22:19PM +0100, H. Peter Anvin wrote:
> On 04/23/2014 09:52 AM, Will Deacon wrote:
> > diff --git a/include/asm-generic/word-at-a-time.h
> > b/include/asm-generic/word-at-a-time.h
> > index d3909effd725..d96deb443f18 100644
> > ---
On Thu, Jan 08, 2015 at 09:54:58AM +, Ard Biesheuvel wrote:
> The early ioremap support introduced by patch bf4b558eba92
> ("arm64: add early_ioremap support") failed to add a call to
> early_ioremap_reset() at an appropriate time. Without this call,
> invocations of early_ioremap etc. that are
On Sun, Jan 11, 2015 at 02:32:30PM +, Roman Pen wrote:
> thread_info->syscall is used only for ptrace, but syscall number
> is also used by syscall_get_nr and returned to userspace by the
> following proc file access:
>
> $ cat /proc/self/syscall
> 0 0x3 0xbe928bd8 0x1000 0x0 0xac9e0 0x3 0xb
On Fri, Jan 16, 2015 at 11:54:45PM +, Kees Cook wrote:
> On Fri, Jan 16, 2015 at 11:57 AM, Kees Cook wrote:
> > On Fri, Jan 16, 2015 at 8:17 AM, Russell King - ARM Linux
> > wrote:
> >> On Sat, Jan 17, 2015 at 01:08:11AM +0900, Roman Peniaev wrote:
> >>> On Sat, Jan 17, 2015 at 12:59 AM, Russ
tracking this one down.
Fixes: e1a5848e3398 ("ARM: 7924/1: mm: don't bother with reserved ttbr0 when
running with LPAE")
Cc: # v3.14+
Reported-by: Raymond Ngun
Tested-by: Raymond Ngun
Reviewed-by: Gregory Fong
Signed-off-by: Will Deacon
---
arch/arm/mm/context.c | 26 +++
; >process has to use the same range again
> > * ...and again, what might lead to looping forever
> >
> > So, remove cacheflush restarting code and terminate cache flushing
> > as early as fatal signal is pending.
> >
> > Cc: stable@vger.kernel.org # 3.1
ate to the correct value.
Cc: # 4.0+
Reported-by: Varun Sethi
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index dce041b1c139..9f1af00d0f68 100644
--- a/drivers/iommu/
On Sun, Jun 14, 2015 at 05:13:05PM +0100, zichao wrote:
> I and marc are talking about how to plug the guest debug exploit in an
> easier way.
>
> I remembered that you mentioned disabling monitor mode had proven to be
> extremely fragile in practice on 32-bit ARM SoCs, what if I save/restore
> th
ate to the correct value.
Cc: # 4.0+
Reported-by: Varun Sethi
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index dce041b1c139..4cd0c29cb585 100644
--- a/drivers/iommu/
Dammit guys, it's never simple is it?
On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote:
> To that end, the herd tool can make a diagram of what it thought
> happened, and I have attached it. I used this diagram to try and force
> this scenario at https://www.cl.cam.ac.uk/~pes20/pp
On Thu, Oct 15, 2015 at 11:35:10AM +0100, Will Deacon wrote:
> Dammit guys, it's never simple is it?
I re-read this and it's even more confusing than I first thought.
> On Wed, Oct 14, 2015 at 02:44:53PM -0700, Paul E. McKenney wrote:
> > To that end, the herd tool can mak
d-off-by: Will Deacon
---
drivers/iommu/arm-smmu-v3.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 637014ab8965..970d78dcac53 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu
Brian Starkey
Tested-by: Brian Starkey
Signed-off-by: Will Deacon
---
Joerg, could you queue this up for 4.3 please? It's a fix, but it's late
in the day for 4.2 and doesn't backport cleanly. Merging it with the Cc
stable tag is probably the easiest thing to do, then I can fix
rinas
Reported-by: Hanjun Guo
Signed-off-by: Will Deacon
---
arch/arm64/kernel/entry.S | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 301c37207c64..2a5e64ccc991 100644
--- a/arch/arm64/kernel/entry.S
On Wed, Aug 19, 2015 at 05:03:20PM +0100, Catalin Marinas wrote:
> On Wed, Aug 19, 2015 at 04:09:49PM +0100, Will Deacon wrote:
> > @@ -613,13 +609,14 @@ ENDPROC(cpu_switch_to)
> > */
> > ret_fast_syscall:
> > disable_irq // disable in
On Wed, Aug 19, 2015 at 05:35:05PM +0100, Catalin Marinas wrote:
> On Wed, Aug 19, 2015 at 05:23:59PM +0100, Will Deacon wrote:
> > On Wed, Aug 19, 2015 at 05:03:20PM +0100, Catalin Marinas wrote:
> > > There is another str x0 in __sys_trace_return which I think we could
> >
On Thu, Aug 20, 2015 at 09:42:12AM +0100, Hanjun Guo wrote:
> On 08/20/2015 12:56 AM, Will Deacon wrote:
> > On Wed, Aug 19, 2015 at 05:35:05PM +0100, Catalin Marinas wrote:
> >> On Wed, Aug 19, 2015 at 05:23:59PM +0100, Will Deacon wrote:
> >>> On Wed, Aug 19, 201
-ordering our restoration of the
AArch32 register aliases so that they happen before the AArch64 system
registers. Ensuring that the registers are restored in this order
guarantees that they will be correctly synchronised by the core.
Cc:
Cc: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm64
On Mon, Sep 14, 2015 at 04:46:28PM +0100, Marc Zyngier wrote:
> On 14/09/15 16:06, Will Deacon wrote:
> > When restoring the system register state for an AArch32 guest at EL2,
> > writes to DACR32_EL2 may not be correctly synchronised by Cortex-A57,
> > which can lead to
On Fri, Jul 13, 2012 at 08:59:39AM +0100, Shawn Guo wrote:
> > diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> > index 8f46446..7babc3f 100644
> > --- a/arch/arm/kernel/smp.c
> > +++ b/arch/arm/kernel/smp.c
> > @@ -590,7 +590,8 @@ void smp_send_stop(void)
> >
> > cpumask_copy(&ma
-off-by: Will Deacon
KernelVersion: 3.5-rc7
---
arch/arm/include/asm/cacheflush.h |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/cacheflush.h
b/arch/arm/include/asm/cacheflush.h
index 004c1bc..8cf828e 100644
--- a/arch/arm/include/asm
TLS pointer).
Cc: # 3.4+
Reported-by: Gilles Chanteperdrix
Tested-by: Uros Bizjak
Signed-off-by: Will Deacon
KernelVersion: 3.5-rc7
---
arch/arm/include/asm/cacheflush.h |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/cacheflush.h
b/arch
VFPv4 support depends on the VFPv3 context save/restore code, so only
advertise support in the hwcaps if the kernel can actually handle it.
Cc: # 3.1+
Signed-off-by: Will Deacon
KernelVersion: 3.6-rc1
---
arch/arm/vfp/vfpmodule.c |2 ++
1 files changed, 2 insertions(+), 0 deletions
the fastpath, ensuring that
any blocked waiters are woken up when the mutex is released.
Cc: Arnd Bergmann
Cc: Thomas Gleixner
Cc: Chris Mason
Cc: Ingo Molnar
Cc: Nicolas Pitre
Cc:
Signed-off-by: Will Deacon
---
Nico: Can I add your S-o-B to this please? Also, preliminary benchmarks
are actually present.
Cc:
Reviewed-by: Catalin Marinas
Signed-off-by: Will Deacon
KernelVersion: 3.6-rc1
---
arch/arm/include/asm/pgtable.h | 34 ++
arch/arm/mm/flush.c|2 --
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch
for the type field. Furthermore, the core code
defines MAX_SWAPFILES_SHIFT as 5, so the additional type bit does not
get used.
This patch reduces the width of the type field to 5 bits, allowing us
to create up to 31 swapfiles of 64GB each.
Cc:
Reviewed-by: Catalin Marinas
Signed-off-by: Will
r platform we must take care to preserve the ASID as the
workaround is not required.
This patch ensures that we don't set the ASID to 0 when flushing the TLB
on such a system, preserving the original behaviour with the workaround
disabled.
Cc:
Signed-off-by: Will Deacon
KernelVersion: 3.6-rc
On Fri, Oct 19, 2012 at 07:19:27AM +0100, Alexander Holler wrote:
> Hello,
>
> Am 18.10.2012 14:16, schrieb Thomas Meyer:
>
> > ERROR: "read_current_timer" [drivers/gpu/drm/udl/udl.ko] undefined!
> > ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
>
> There is already a long thread abo
ly used on affected
cores, which are known to be UP only. Other v6 cores can rely on the
FSR to indicate the access type correctly.
Cc: stable@vger.kernel.org
Signed-off-by: Will Deacon
KernelVersion: 3.4-rc3
---
arch/arm/Kconfig|9 +
arch/arm/mm/abort-ev6.S | 17 ++
The workaround for PL310 erratum #753970 can lead to deadlock on systems
with an L220 cache controller.
This patch makes the workaround effective only when the cache controller
is identified as a PL310 at probe time.
Cc: stable@vger.kernel.org
Signed-off-by: Will Deacon
KernelVersion: 3.4-rc3
-off-by: Will Deacon
KernelVersion: 3.4-rc3
---
arch/arm/mm/cache-l2x0.c | 13 -
1 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index a8d02c0..2a8e380 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache
saving
and restoring it) will not cause any problems to userspace.
Cc: stable@vger.kernel.org
Signed-off-by: Will Deacon
KernelVersion: 3.4-rc4
---
arch/arm/include/asm/tls.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include
_stop, therefore ensuring that it executes on the
killing CPU rather than on the victim, matching what the hotplug code
requires.
Cc: stable@vger.kernel.org
Reported-by: Russell King
Signed-off-by: Will Deacon
KernelVersion: 3.4-rc4
---
arch/arm/kernel/smp.c | 28 +---
1
may confuse userspace IRQ balancing daemons.
This patch updates migrate_one_irq to copy the affinity mask when
the interrupt chip returns IRQ_SET_MASK_OK after forcefully changing the
affinity of an interrupt.
Cc: stable@vger.kernel.org
Reported-by: Leif Lindholm
Signed-off-by: Will Deacon
sed by the flush itself,
get rid of vma as an argument.
Cc: stable@vger.kernel.org
Acked-by: Catalin Marinas
Signed-off-by: Dima Zavin
Signed-off-by: John Stultz
Signed-off-by: Will Deacon
KernelVersion: 3.4-rc4
---
arch/arm/include/asm/cacheflush.h |2 +-
arch/arm/kernel/traps.c
patch fixes the syscall tracing code so that the why parameter is
used to infer the syscall direction and the saved ip is only updated if
we know that we will be signalling a ptrace trap.
Cc: stable@vger.kernel.org
Cc: Eric Paris
Reported-and-tested-by: Jon Masters
Signed-off-by: Will Deacon
The machine endianness has no direct correspondence to the syscall ABI,
so use only AUDIT_ARCH_ARM when identifying the ABI to the audit tools
in userspace.
Cc: stable@vger.kernel.org
Signed-off-by: Will Deacon
KernelVersion: 3.4-rc5
---
arch/arm/kernel/ptrace.c |8 +---
1 files
ctive only when the cache controller
> is identified as a PL310 at probe time.
>
> Signed-off-by: Will Deacon
> Signed-off-by: Russell King
> [bwh: Backported to 3.2: adjust context]
> Signed-off-by: Ben Hutchings
> ---
> arch/arm/mm/cache-l2x0.c | 12 ++--
365/1)]
Cc: # 2.6.32+: 4542b6a0: ARM: 7365/1
Cc: # 2.6.32+
Acked-by: Catalin Marinas
Signed-off-by: Dima Zavin
Signed-off-by: John Stultz
Signed-off-by: Will Deacon
Signed-off-by: Russell King
---
Greg: This patch is a candidate for -stable, but its dependency (listed
above) wasn
therefore preventing the thread from being updated with stale data on
the next context switch.
Cc: stable
Tested-by: Peter Maydell
Signed-off-by: Will Deacon
KernelVersion: 3.3-rc1
---
arch/arm/kernel/signal.c |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/
ore reading
thread->vfpstate, to make sure that the thread's VFP state is not
live in the hardware registers while the registers are modified.
Thanks to Will Deacon for spotting this.
Cc: stable
Signed-off-by: Dave Martin
Signed-off-by: Will Deacon
KernelVersion: 3.3-rc1
---
arch
thread state is
flushed before the copy, therefore disabling VFP and preventing
corruption from occurring.
Cc: stable
Signed-off-by: Will Deacon
KernelVersion: 3.3-rc1
---
arch/arm/kernel/ptrace.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/kernel/ptra
Hi Ben,
On Wed, Aug 15, 2012 at 05:29:26AM +0100, Ben Hutchings wrote:
> On Mon, 2012-08-13 at 15:13 -0700, Greg Kroah-Hartman wrote:
> > From: Greg KH
> >
> > 3.4-stable review patch. If anyone has any objections, please let me know.
> >
> > ----
On Wed, Aug 15, 2012 at 03:49:56PM +0100, Greg Kroah-Hartman wrote:
> > Will Deacon wrote:
> > > The additional patch should also be CC'd to stable and is sitting in -tip
> > > somewhere I believe, so it shouldn't be long before it does hit mainline.
> &g
no impact.
Cc:
Signed-off-by: Will Deacon
KernelVersion: 3.6-rc1
---
arch/arm/kernel/hw_breakpoint.c | 55 --
1 files changed, 40 insertions(+), 15 deletions(-)
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index ba38
On Wed, Aug 22, 2012 at 03:52:18PM +0100, Shawn Guo wrote:
> diff --git a/arch/arm/include/asm/processor.h
> b/arch/arm/include/asm/processor.h
> index 99afa74..7cc67ce 100644
> --- a/arch/arm/include/asm/processor.h
> +++ b/arch/arm/include/asm/processor.h
> @@ -80,7 +80,14 @@ extern void release
n for mutexes on
ARMv6+, which introduces barriers to the lock/unlock operations and also
has the benefit of removing a fair amount of inline assembly code.
Cc: : 0bce9c46: mutex: Place lock in contended...
Cc:
Acked-by: Arnd Bergmann
Acked-by: Nicolas Pitre
Reported-by: Shan Kang
Signed-off-by:
Signed-off-by: Will Deacon
KernelVersion: 3.6-rc3
---
arch/arm/boot/compressed/head.S |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b8c64b8..81769c1 100644
--- a/arch/arm/boot/compressed/head.S
+++ b
Commit-ID: 0bce9c46bf3b15f485d82d7e81dabed6ebcc24b1
Gitweb: http://git.kernel.org/tip/0bce9c46bf3b15f485d82d7e81dabed6ebcc24b1
Author: Will Deacon
AuthorDate: Fri, 10 Aug 2012 15:22:09 +0100
Committer: Thomas Gleixner
CommitDate: Mon, 13 Aug 2012 18:46:54 +0200
mutex: Place lock in
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