Andi,
On Tue, 8 Sep 2015, Andi Kleen wrote:
> > Hmm, I didn't mean mfence can't serialize the instructions. For a true
> > IO, a serialization can't guarantee device finishes the IO, we generally
> > read some safe IO registers to wait IO finish. I completely don't know
> > if this case fits
> Hmm, I didn't mean mfence can't serialize the instructions. For a true
> IO, a serialization can't guarantee device finishes the IO, we generally
> read some safe IO registers to wait IO finish. I completely don't know
> if this case fits here though.
Sorry for the late answer. We (Intel)
72d607814d9e808d05765 Mon Sep 17 00:00:00 2001
Message-Id:
<b5cdd3c14b0589e5d5a72d607814d9e808d05765.1441771848.git.s...@fb.com>
From: Shaohua Li <s...@fb.com>
Date: Thu, 30 Jul 2015 16:24:43 -0700
Subject: [PATCH] x86: serialize LVTT and TSC_DEADLINE write
We saw a strange issue with local APIC timer. Some random CPU d
* Shaohua Li s...@fb.com wrote:
On Sun, Aug 02, 2015 at 09:41:08PM +0200, Thomas Gleixner wrote:
On Sun, 2 Aug 2015, Shaohua Li wrote:
On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote:
On Fri, 31 Jul 2015, Shaohua Li wrote:
@@ -336,6 +336,22 @@ static void
On Wed, Aug 05, 2015 at 10:44:24AM +0200, Ingo Molnar wrote:
* Shaohua Li s...@fb.com wrote:
On Sun, Aug 02, 2015 at 09:41:08PM +0200, Thomas Gleixner wrote:
On Sun, 2 Aug 2015, Shaohua Li wrote:
On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote:
On Fri, 31 Jul
On Sun, Aug 02, 2015 at 09:41:08PM +0200, Thomas Gleixner wrote:
On Sun, 2 Aug 2015, Shaohua Li wrote:
On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote:
On Fri, 31 Jul 2015, Shaohua Li wrote:
@@ -336,6 +336,22 @@ static void __setup_APIC_LVTT(unsigned int clocks,
On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote:
On Fri, 31 Jul 2015, Shaohua Li wrote:
@@ -336,6 +336,22 @@ static void __setup_APIC_LVTT(unsigned int clocks, int
oneshot, int irqen)
apic_write(APIC_LVTT, lvtt_value);
if (lvtt_value
On Sun, 2 Aug 2015, Shaohua Li wrote:
On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote:
On Fri, 31 Jul 2015, Shaohua Li wrote:
@@ -336,6 +336,22 @@ static void __setup_APIC_LVTT(unsigned int clocks,
int oneshot, int irqen)
apic_write(APIC_LVTT, lvtt_value);
On Fri, 31 Jul 2015, Shaohua Li wrote:
@@ -336,6 +336,22 @@ static void __setup_APIC_LVTT(unsigned int clocks, int
oneshot, int irqen)
apic_write(APIC_LVTT, lvtt_value);
if (lvtt_value APIC_LVT_TIMER_TSCDEADLINE) {
+ u64 msr;
+
+ /*
+ *
We saw a strange issue with local APIC timer. Some random CPU doesn't
receive any local APIC timer interrupt, which causes different issues.
The cpu uses TSC-Deadline mode for local APIC timer and APIC is in xAPIC
mode. When this happens, manually writing TSC_DEADLINE MSR can trigger
interrupt
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