3.10-stable review patch. If anyone has any objections, please let me know.
------------------
From: Taras Kondratiuk <taras.kondrat...@linaro.org>
commit b25f3e1c358434bf850220e04f28eebfc45eb634 upstream.
Kexec disables outer cache before jumping to reboot code, but it doesn't
flush it explicitly. Flush is done implicitly inside of l2x0_disable().
But some SoC's override default .disable handler and don't flush cache.
This may lead to a corrupted memory during Kexec reboot on these
platforms.
This patch adds cache flush inside of OMAP4 and Highbank outer_cache.disable()
handlers to make it consistent with default l2x0_disable().
Acked-by: Rob Herring <rob.herr...@calxeda.com>
Acked-by: Santosh Shilimkar <santosh.shilim...@ti.com>
Acked-by: Tony Lindgren <t...@atomide.com>
Signed-off-by: Taras Kondratiuk <taras.kondrat...@linaro.org>
Signed-off-by: Russell King <rmk+ker...@arm.linux.org.uk>
Cc: Wang Nan <wangn...@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
---
arch/arm/mach-highbank/highbank.c | 1 +
arch/arm/mach-omap2/omap4-common.c | 1 +
2 files changed, 2 insertions(+)
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -68,6 +68,7 @@ void highbank_set_cpu_jump(int cpu, void
#ifdef CONFIG_CACHE_L2X0
static void highbank_l2x0_disable(void)
{
+ outer_flush_all();
/* Disable PL310 L2 Cache controller */
highbank_smc1(0x102, 0x0);
}
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -162,6 +162,7 @@ void __iomem *omap4_get_l2cache_base(voi
static void omap4_l2x0_disable(void)
{
+ outer_flush_all();
/* Disable PL310 L2 Cache controller */
omap_smc1(0x102, 0x0);
}
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