Author: ian
Date: Wed May 14 17:40:18 2014
New Revision: 266058
URL: http://svnweb.freebsd.org/changeset/base/266058
Log:
MFC r258359, r258742, r258845, r259936, r259640
Apply access flags for managed and unmanaged pages properly on ARMv6/v7
Set the PGA_WRITEABLE flag when the protections indicate write access, not
just when the current access is a write.
Enable missing Access Flag for secondary cores on ARMv6/v7
Add identification and necessary type checks for Krait CPU cores.
Modified:
stable/10/sys/arm/arm/cpufunc.c
stable/10/sys/arm/arm/elf_trampoline.c
stable/10/sys/arm/arm/identcpu.c
stable/10/sys/arm/arm/locore.S
stable/10/sys/arm/arm/pmap-v6.c
stable/10/sys/arm/arm/swtch.S
stable/10/sys/arm/include/armreg.h
stable/10/sys/arm/include/cpuconf.h
stable/10/sys/arm/include/cpufunc.h
stable/10/sys/arm/include/intr.h
stable/10/sys/arm/include/md_var.h
stable/10/sys/conf/files.arm
stable/10/sys/conf/options.arm
Directory Properties:
stable/10/ (props changed)
Modified: stable/10/sys/arm/arm/cpufunc.c
==============================================================================
--- stable/10/sys/arm/arm/cpufunc.c Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/arm/arm/cpufunc.c Wed May 14 17:40:18 2014
(r266058)
@@ -1038,7 +1038,7 @@ struct cpu_functions arm1176_cpufuncs =
};
#endif /*CPU_ARM1176 */
-#if defined(CPU_CORTEXA)
+#if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
struct cpu_functions cortexa_cpufuncs = {
/* CPU functions */
@@ -1118,7 +1118,7 @@ u_int cpu_reset_needs_v4_MMU_disable; /*
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_FA526) || defined(CPU_FA626TE) || defined(CPU_MV_PJ4B) ||
\
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
- defined(CPU_CORTEXA)
+ defined(CPU_CORTEXA) || defined(CPU_KRAIT)
static void get_cachetype_cp15(void);
@@ -1416,7 +1416,7 @@ set_cpufuncs()
goto out;
}
#endif /* CPU_ARM1136 || CPU_ARM1176 */
-#ifdef CPU_CORTEXA
+#if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
if (cputype == CPU_ID_CORTEXA7 ||
cputype == CPU_ID_CORTEXA8R1 ||
cputype == CPU_ID_CORTEXA8R2 ||
@@ -1424,7 +1424,8 @@ set_cpufuncs()
cputype == CPU_ID_CORTEXA9R1 ||
cputype == CPU_ID_CORTEXA9R2 ||
cputype == CPU_ID_CORTEXA9R3 ||
- cputype == CPU_ID_CORTEXA15 ) {
+ cputype == CPU_ID_CORTEXA15 ||
+ cputype == CPU_ID_KRAIT ) {
cpufuncs = cortexa_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
get_cachetype_cp15();
@@ -2406,7 +2407,7 @@ pj4bv7_setup(args)
}
#endif /* CPU_MV_PJ4B */
-#ifdef CPU_CORTEXA
+#if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
void
cortexa_setup(char *args)
Modified: stable/10/sys/arm/arm/elf_trampoline.c
==============================================================================
--- stable/10/sys/arm/arm/elf_trampoline.c Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/arm/arm/elf_trampoline.c Wed May 14 17:40:18 2014
(r266058)
@@ -102,7 +102,7 @@ extern void xscalec3_l2cache_purge(void)
#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
#define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all
extern void sheeva_l2cache_wbinv_all(void);
-#elif defined(CPU_CORTEXA)
+#elif defined(CPU_CORTEXA) || defined(CPU_KRAIT)
#define cpu_idcache_wbinv_all armv7_idcache_wbinv_all
#define cpu_l2cache_wbinv_all()
#else
Modified: stable/10/sys/arm/arm/identcpu.c
==============================================================================
--- stable/10/sys/arm/arm/identcpu.c Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/arm/arm/identcpu.c Wed May 14 17:40:18 2014
(r266058)
@@ -252,6 +252,8 @@ const struct cpuidtab cpuids[] = {
generic_steppings },
{ CPU_ID_CORTEXA15, CPU_CLASS_CORTEXA, "Cortex A15",
generic_steppings },
+ { CPU_ID_KRAIT, CPU_CLASS_KRAIT, "Krait",
+ generic_steppings },
{ CPU_ID_SA110, CPU_CLASS_SA1, "SA-110",
sa110_steppings },
@@ -351,6 +353,7 @@ const struct cpu_classtab cpu_classes[]
{ "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */
{ "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */
{ "Cortex-A", "CPU_CORTEXA" }, /* CPU_CLASS_CORTEXA */
+ { "Krait", "CPU_KRAIT" }, /* CPU_CLASS_KRAIT */
{ "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */
{ "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */
{ "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */
Modified: stable/10/sys/arm/arm/locore.S
==============================================================================
--- stable/10/sys/arm/arm/locore.S Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/arm/arm/locore.S Wed May 14 17:40:18 2014
(r266058)
@@ -170,7 +170,7 @@ Lunmapped:
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) ||
defined(CPU_MV_PJ4B)
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) ||
defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
#endif
@@ -377,7 +377,7 @@ Ltag:
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) ||
defined(CPU_CORTEXA)
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) ||
defined(CPU_CORTEXA) || defined(CPU_KRAIT)
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
#endif
@@ -389,8 +389,9 @@ Ltag:
mcr p15, 0, r0, c3, c0, 0
/* Enable MMU */
mrc p15, 0, r0, c1, c0, 0
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) ||
defined(CPU_CORTEXA)
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) ||
defined(CPU_CORTEXA) || defined(CPU_KRAIT)
orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
+ orr r0, r0, #CPU_CONTROL_AF_ENABLE
#endif
orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
mcr p15, 0, r0, c1, c0, 0
Modified: stable/10/sys/arm/arm/pmap-v6.c
==============================================================================
--- stable/10/sys/arm/arm/pmap-v6.c Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/arm/arm/pmap-v6.c Wed May 14 17:40:18 2014
(r266058)
@@ -3079,31 +3079,33 @@ validate:
* then continue setting mapping parameters
*/
if (m != NULL) {
- if (prot & (VM_PROT_ALL)) {
- if ((m->oflags & VPO_UNMANAGED) == 0)
+ if ((m->oflags & VPO_UNMANAGED) == 0) {
+ if (prot & (VM_PROT_ALL)) {
vm_page_aflag_set(m, PGA_REFERENCED);
- } else {
- /*
- * Need to do page referenced emulation.
- */
- npte &= ~L2_S_REF;
+ } else {
+ /*
+ * Need to do page referenced emulation.
+ */
+ npte &= ~L2_S_REF;
+ }
}
if (prot & VM_PROT_WRITE) {
- /* Write enable */
- npte &= ~(L2_APX);
-
if ((m->oflags & VPO_UNMANAGED) == 0) {
vm_page_aflag_set(m, PGA_WRITEABLE);
/*
- * The access type and permissions indicate
- * that the page will be written as soon as
- * returned from fault service.
- * Mark it dirty from the outset.
+ * XXX: Skip modified bit emulation for now.
+ * The emulation reveals problems
+ * that result in random failures
+ * during memory allocation on some
+ * platforms.
+ * Therefore, the page is marked RW
+ * immediately.
*/
- if ((access & VM_PROT_WRITE) != 0)
- vm_page_dirty(m);
- }
+ npte &= ~(L2_APX);
+ vm_page_dirty(m);
+ } else
+ npte &= ~(L2_APX);
}
if (!(prot & VM_PROT_EXECUTE))
npte |= L2_XN;
Modified: stable/10/sys/arm/arm/swtch.S
==============================================================================
--- stable/10/sys/arm/arm/swtch.S Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/arm/arm/swtch.S Wed May 14 17:40:18 2014
(r266058)
@@ -131,7 +131,7 @@ ENTRY(cpu_throw)
/* Switch to lwp0 context */
ldr r9, .Lcpufuncs
-#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
+#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) &&
!defined(CPU_KRAIT)
mov lr, pc
ldr pc, [r9, #CF_IDCACHE_WBINV_ALL]
#endif
@@ -361,7 +361,7 @@ ENTRY(cpu_switch)
cmpeq r0, r5 /* Same DACR? */
beq .Lcs_context_switched /* yes! */
-#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
+#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) &&
!defined(CPU_KRAIT)
/*
* Definately need to flush the cache.
*/
Modified: stable/10/sys/arm/include/armreg.h
==============================================================================
--- stable/10/sys/arm/include/armreg.h Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/arm/include/armreg.h Wed May 14 17:40:18 2014
(r266058)
@@ -157,6 +157,7 @@
#define CPU_ID_CORTEXA15 0x410fc0f0
#define CPU_ID_SA110 0x4401a100
#define CPU_ID_SA1100 0x4401a110
+#define CPU_ID_KRAIT 0x510f06f0 /* Snapdragon S4 Pro/APQ8064
*/
#define CPU_ID_TI925T 0x54029250
#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */
#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */
Modified: stable/10/sys/arm/include/cpuconf.h
==============================================================================
--- stable/10/sys/arm/include/cpuconf.h Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/arm/include/cpuconf.h Wed May 14 17:40:18 2014
(r266058)
@@ -66,6 +66,7 @@
defined(CPU_FA626TE) + \
defined(CPU_XSCALE_IXP425)) + \
defined(CPU_CORTEXA) + \
+ defined(CPU_KRAIT) + \
defined(CPU_MV_PJ4B)
/*
@@ -97,7 +98,7 @@
#endif
#endif
-#if defined(CPU_CORTEXA)
+#if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
#define ARM_ARCH_7A 1
#else
#define ARM_ARCH_7A 0
@@ -156,7 +157,7 @@
#define ARM_MMU_V6 0
#endif
-#if defined(CPU_CORTEXA)
+#if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
#define ARM_MMU_V7 1
#else
#define ARM_MMU_V7 0
Modified: stable/10/sys/arm/include/cpufunc.h
==============================================================================
--- stable/10/sys/arm/include/cpufunc.h Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/arm/include/cpufunc.h Wed May 14 17:40:18 2014
(r266058)
@@ -188,7 +188,7 @@ extern u_int cputype;
#else
void tlb_broadcast(int);
-#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
+#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
#define TLB_BROADCAST /* No need to explicitely send an IPI */
#else
#define TLB_BROADCAST tlb_broadcast(7)
@@ -463,7 +463,7 @@ void sheeva_l2cache_wbinv_all (void);
#endif
#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \
- defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
+ defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
void arm11_setttb (u_int);
void arm11_sleep (int);
Modified: stable/10/sys/arm/include/intr.h
==============================================================================
--- stable/10/sys/arm/include/intr.h Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/arm/include/intr.h Wed May 14 17:40:18 2014
(r266058)
@@ -52,6 +52,8 @@
#define NIRQ 64
#elif defined(CPU_CORTEXA)
#define NIRQ 160
+#elif defined(CPU_KRAIT)
+#define NIRQ 288
#elif defined(CPU_ARM1136) || defined(CPU_ARM1176)
#define NIRQ 128
#elif defined(SOC_MV_ARMADAXP)
Modified: stable/10/sys/arm/include/md_var.h
==============================================================================
--- stable/10/sys/arm/include/md_var.h Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/arm/include/md_var.h Wed May 14 17:40:18 2014
(r266058)
@@ -63,6 +63,7 @@ enum cpu_class {
CPU_CLASS_ARM10E,
CPU_CLASS_ARM10EJ,
CPU_CLASS_CORTEXA,
+ CPU_CLASS_KRAIT,
CPU_CLASS_SA1,
CPU_CLASS_XSCALE,
CPU_CLASS_ARM11J,
Modified: stable/10/sys/conf/files.arm
==============================================================================
--- stable/10/sys/conf/files.arm Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/conf/files.arm Wed May 14 17:40:18 2014
(r266058)
@@ -6,7 +6,7 @@ arm/arm/blockio.S standard
arm/arm/bootconfig.c standard
arm/arm/bus_space_asm_generic.S standard
arm/arm/busdma_machdep.c optional cpu_arm9 | cpu_arm9e |
cpu_fa526 | cpu_sa1100 | cpu_sa1110 | cpu_xscale_80219 | cpu_xscale_80321 |
cpu_xscale_81342 | cpu_xscale_ixp425 | cpu_xscale_ixp435 | cpu_xscale_pxa2x0
-arm/arm/busdma_machdep-v6.c optional cpu_arm1136 | cpu_arm1176 |
cpu_cortexa | cpu_mv_pj4b
+arm/arm/busdma_machdep-v6.c optional cpu_arm1136 | cpu_arm1176 |
cpu_cortexa | cpu_mv_pj4b | cpu_krait
arm/arm/copystr.S standard
arm/arm/cpufunc.c standard
arm/arm/cpufunc_asm.S standard
@@ -36,7 +36,7 @@ arm/arm/nexus.c standard
arm/arm/pl190.c optional pl190
arm/arm/pl310.c optional pl310
arm/arm/pmap.c optional cpu_arm9 | cpu_arm9e |
cpu_fa526 | cpu_sa1100 | cpu_sa1110 | cpu_xscale_80219 | cpu_xscale_80321 |
cpu_xscale_81342 | cpu_xscale_ixp425 | cpu_xscale_ixp435 | cpu_xscale_pxa2x0
-arm/arm/pmap-v6.c optional cpu_arm1136 | cpu_arm1176 |
cpu_cortexa | cpu_mv_pj4b
+arm/arm/pmap-v6.c optional cpu_arm1136 | cpu_arm1176 |
cpu_cortexa | cpu_mv_pj4b | cpu_krait
arm/arm/sc_machdep.c optional sc
arm/arm/setcpsr.S standard
arm/arm/setstack.s standard
Modified: stable/10/sys/conf/options.arm
==============================================================================
--- stable/10/sys/conf/options.arm Wed May 14 17:28:49 2014
(r266057)
+++ stable/10/sys/conf/options.arm Wed May 14 17:40:18 2014
(r266058)
@@ -13,6 +13,7 @@ CPU_ARM9E opt_global.h
CPU_ARM1136 opt_global.h
CPU_ARM1176 opt_global.h
CPU_CORTEXA opt_global.h
+CPU_KRAIT opt_global.h
CPU_FA526 opt_global.h
CPU_FA626TE opt_global.h
CPU_MV_PJ4B opt_global.h
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