Author: bz
Date: Sat Aug 16 14:30:46 2014
New Revision: 270061
URL: http://svnweb.freebsd.org/changeset/base/270061
Log:
MFC r264601,264646,265766,267918,267919,267920:
Merge if_nf10bmac(4), a driver to support an NetFPGA-10G Embedded
CPU Ethernet Core.
The current version operates on a simple PIO based interface connected
to a NetFPGA-10G port.
To avoid confusion: this driver operates on a CPU running on the FPGA,
e.g. BERI/mips, and is not suited for the PCI host interface.
Adjust the register layout to allow for 64bit registers in the
future for nf10bmac(4). Also, add support for and enable RX interrupts.
Allow switching between 32bit and 64bit bus width data access at compile
time by setting NF10BMAC_64BIT and using a REGWTYPE #define to set correct
variable and return value widths.
Adjust comments to indicate the 32 or 64bit register widths.
Relnotes: yes
Sponsored by: DARPA/AFRL
Added:
stable/10/share/man/man4/netfpga10g_nf10bmac.4
- copied unchanged from r264601, head/share/man/man4/netfpga10g_nf10bmac.4
stable/10/sys/dev/netfpga10g/
- copied from r264601, head/sys/dev/netfpga10g/
stable/10/sys/modules/netfpga10g/
- copied from r264601, head/sys/modules/netfpga10g/
Modified:
stable/10/share/man/man4/Makefile
stable/10/sys/boot/fdt/dts/mips/beri-netfpga.dts
stable/10/sys/dev/netfpga10g/nf10bmac/if_nf10bmac.c
stable/10/sys/dev/netfpga10g/nf10bmac/if_nf10bmac_fdt.c
stable/10/sys/dev/netfpga10g/nf10bmac/if_nf10bmacreg.h
stable/10/sys/mips/beri/files.beri
stable/10/sys/mips/conf/BERI_NETFPGA_MDROOT
stable/10/sys/modules/Makefile
Directory Properties:
stable/10/ (props changed)
Modified: stable/10/share/man/man4/Makefile
==============================================================================
--- stable/10/share/man/man4/Makefile Sat Aug 16 14:21:03 2014
(r270060)
+++ stable/10/share/man/man4/Makefile Sat Aug 16 14:30:46 2014
(r270061)
@@ -282,6 +282,7 @@ MAN= aac.4 \
ncv.4 \
${_ndis.4} \
net80211.4 \
+ netfpga10g_nf10bmac.4 \
netgraph.4 \
netintro.4 \
netmap.4 \
@@ -678,6 +679,7 @@ MLINKS+=mwl.4 if_mwl.4
MLINKS+=mxge.4 if_mxge.4
MLINKS+=my.4 if_my.4
MLINKS+=${_ndis.4} ${_if_ndis.4}
+MLINKS+=netfpga10g_nf10bmac.4 if_nf10bmac.4
MLINKS+=netintro.4 net.4 \
netintro.4 networking.4
MLINKS+=${_nfe.4} ${_if_nfe.4}
Copied: stable/10/share/man/man4/netfpga10g_nf10bmac.4 (from r264601,
head/share/man/man4/netfpga10g_nf10bmac.4)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ stable/10/share/man/man4/netfpga10g_nf10bmac.4 Sat Aug 16 14:30:46
2014 (r270061, copy of r264601,
head/share/man/man4/netfpga10g_nf10bmac.4)
@@ -0,0 +1,70 @@
+.\"-
+.\" Copyright (c) 2014 Bjoern A. Zeeb
+.\" All rights reserved.
+.\"
+.\" This software was developed by SRI International and the University of
+.\" Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249
+.\" ("MRC2"), as part of the DARPA MRC research programme.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd April 17, 2014
+.Dt NETFPGA10G_NF10BMAC 4
+.Os
+.Sh NAME
+.Nm netfpga10g_nf10bmac
+.Nd driver for the NetFPGA-10G Embedded CPU Ethernet Core
+.Sh SYNOPSIS
+.Cd "device netfpga10g_nf10bmac"
+.Sh DESCRIPTION
+The
+.Nm
+device driver provides support for the NetFPGA-10G Embedded CPU Ethernet
+Core.
+.Sh HARDWARE
+The current version of the
+.Nm
+driver works with one PIO mode interface of the
+NetFPGA-10G Embedded CPU Ethernet Core version 1.00a.
+.Sh SEE ALSO
+.Xr netintro 4 ,
+.Xr ifconfig 8
+.Rs
+.%T NetFPGA-10G Wiki
+.%U https://github.com/NetFPGA/NetFPGA-public/wiki
+.Re
+.Sh HISTORY
+The
+.Nm
+device driver first appeared in
+.Fx 11.0 .
+.Sh AUTHORS
+This software and this manual page were
+developed by SRI International and the University of Cambridge Computer
+Laboratory under DARPA/AFRL contract
+.Pq FA8750-11-C-0249
+.Pq Do MRC2 Dc ,
+as part of the DARPA MRC research programme.
+The device driver was written by
+.An Bjoern A. Zeeb .
Modified: stable/10/sys/boot/fdt/dts/mips/beri-netfpga.dts
==============================================================================
--- stable/10/sys/boot/fdt/dts/mips/beri-netfpga.dts Sat Aug 16 14:21:03
2014 (r270060)
+++ stable/10/sys/boot/fdt/dts/mips/beri-netfpga.dts Sat Aug 16 14:30:46
2014 (r270061)
@@ -1,7 +1,7 @@
/*-
* Copyright (c) 2012-2013 Robert N. M. Watson
* Copyright (c) 2013 SRI International
- * Copyright (c) 2013 Bjoern A. Zeeb
+ * Copyright (c) 2013-2014 Bjoern A. Zeeb
* All rights reserved.
*
* This software was developed by SRI International and the University of
@@ -130,6 +130,18 @@
interrupt-parent = <&beripic>;
};
*/
+
+ ethernet@7f005000 {
+ compatible = "netfpag10g,nf10bmac";
+ // LOOP, TX, RX, INTR
+ reg = <0x7f005000 0x20
+ 0x7f005020 0x30
+ 0x7f005050 0x30
+ 0x7f005100 0x10>;
+ // RX
+ interrupts = <1>;
+ interrupt-parent = <&beripic>;
+ };
};
aliases {
Modified: stable/10/sys/dev/netfpga10g/nf10bmac/if_nf10bmac.c
==============================================================================
--- head/sys/dev/netfpga10g/nf10bmac/if_nf10bmac.c Thu Apr 17 12:33:26
2014 (r264601)
+++ stable/10/sys/dev/netfpga10g/nf10bmac/if_nf10bmac.c Sat Aug 16 14:30:46
2014 (r270061)
@@ -92,13 +92,15 @@ static poll_handler_t nf10bmac_poll;
#define NF10BMAC_LOCK_ASSERT(_sc) \
mtx_assert(&(_sc)->nf10bmac_mtx, MA_OWNED)
-#define NF10BMAC_TX_LEN 0x08
-#define NF10BMAC_TX_META 0x04
+#define NF10BMAC_CTRL0 0x00
#define NF10BMAC_TX_DATA 0x00
-#define NF10BMAC_RX_LEN 0x08
-#define NF10BMAC_RX_META 0x04
+#define NF10BMAC_TX_META 0x08
+#define NF10BMAC_TX_LEN 0x10
#define NF10BMAC_RX_DATA 0x00
-#define NF10BMAC_CTRL0 0x00
+#define NF10BMAC_RX_META 0x08
+#define NF10BMAC_RX_LEN 0x10
+#define NF10BMAC_INTR_CLEAR_DIS 0x00
+#define NF10BMAC_INTR_CTRL 0x08
#define NF10BMAC_TUSER_MAC0 (1 << 0)
#define NF10BMAC_TUSER_CPU0 (1 << 1)
@@ -109,63 +111,101 @@ static poll_handler_t nf10bmac_poll;
#define NF10BMAC_TUSER_MAC3 (1 << 6)
#define NF10BMAC_TUSER_CPU3 (1 << 7)
+#define NF10BMAC_DATA_LEN_MASK 0x0000ffff
#define NF10BMAC_DATA_DPORT_MASK 0xff000000
#define NF10BMAC_DATA_DPORT_SHIFT 24
#define NF10BMAC_DATA_SPORT_MASK 0x00ff0000
#define NF10BMAC_DATA_SPORT_SHIFT 16
-#define NF10BMAC_DATA_LAST 0x00000080
+#define NF10BMAC_DATA_LAST 0x00008000
+#ifdef NF10BMAC_64BIT
+#define NF10BMAC_DATA_STRB 0x000000ff
+#define REGWTYPE uint64_t
+#else
#define NF10BMAC_DATA_STRB 0x0000000f
+#define REGWTYPE uint32_t
+#endif
static inline void
-nf10bmac_write_4(struct resource *res, uint32_t reg, uint32_t val4,
+nf10bmac_write(struct resource *res, REGWTYPE reg, REGWTYPE val,
const char *f __unused, const int l __unused)
{
- bus_write_4(res, reg, htole32(val4));
+#ifdef NF10BMAC_64BIT
+ bus_write_8(res, reg, htole64(val));
+#else
+ bus_write_4(res, reg, htole32(val));
+#endif
}
-static inline uint32_t
-nf10bmac_read_4(struct resource *res, uint32_t reg,
+static inline REGWTYPE
+nf10bmac_read(struct resource *res, REGWTYPE reg,
const char *f __unused, const int l __unused)
{
+#ifdef NF10BMAC_64BIT
+ return (le64toh(bus_read_8(res, reg)));
+#else
return (le32toh(bus_read_4(res, reg)));
+#endif
}
static inline void
-nf10bmac_write_4_be(struct resource *res, uint32_t reg, uint32_t val4,
+nf10bmac_write_be(struct resource *res, REGWTYPE reg, REGWTYPE val,
const char *f __unused, const int l __unused)
{
- bus_write_4(res, reg, htobe32(val4));
+#ifdef NF10BMAC_64BIT
+ bus_write_8(res, reg, htobe64(val));
+#else
+ bus_write_4(res, reg, htobe32(val));
+#endif
}
-static inline uint32_t
-nf10bmac_read_4_be(struct resource *res, uint32_t reg,
+static inline REGWTYPE
+nf10bmac_read_be(struct resource *res, REGWTYPE reg,
const char *f __unused, const int l __unused)
{
+#ifdef NF10BMAC_64BIT
+ return (be64toh(bus_read_8(res, reg)));
+#else
return (be32toh(bus_read_4(res, reg)));
+#endif
}
-#define NF10BMAC_WRITE_CTRL_4(sc, reg, val)
\
- nf10bmac_write_4((sc)->nf10bmac_mem_res, (reg), (val), \
+#define NF10BMAC_WRITE_CTRL(sc, reg, val)
\
+ nf10bmac_write((sc)->nf10bmac_ctrl_res, (reg), (val), \
__func__, __LINE__)
-#define NF10BMAC_WRITE_4(sc, reg, val)
\
- nf10bmac_write_4((sc)->nf10bmac_tx_mem_res, (reg), (val), \
+#define NF10BMAC_WRITE(sc, reg, val)
\
+ nf10bmac_write((sc)->nf10bmac_tx_mem_res, (reg), (val), \
__func__, __LINE__)
-#define NF10BMAC_READ_4(sc, reg)
\
- nf10bmac_read_4((sc)->nf10bmac_rx_mem_res, (reg), \
+#define NF10BMAC_READ(sc, reg)
\
+ nf10bmac_read((sc)->nf10bmac_rx_mem_res, (reg), \
__func__, __LINE__)
-#define NF10BMAC_WRITE_4_BE(sc, reg, val)
\
- nf10bmac_write_4_be((sc)->nf10bmac_tx_mem_res, (reg), (val), \
+#define NF10BMAC_WRITE_BE(sc, reg, val)
\
+ nf10bmac_write_be((sc)->nf10bmac_tx_mem_res, (reg), (val), \
__func__, __LINE__)
-#define NF10BMAC_READ_4_BE(sc, reg)
\
- nf10bmac_read_4_be((sc)->nf10bmac_rx_mem_res, (reg), \
+#define NF10BMAC_READ_BE(sc, reg)
\
+ nf10bmac_read_be((sc)->nf10bmac_rx_mem_res, (reg), \
__func__, __LINE__)
+#define NF10BMAC_WRITE_INTR(sc, reg, val, _f, _l)
\
+ nf10bmac_write((sc)->nf10bmac_intr_res, (reg), (val), \
+ (_f), (_l))
+
+#define NF10BMAC_RX_INTR_CLEAR_DIS(sc)
\
+ NF10BMAC_WRITE_INTR((sc), NF10BMAC_INTR_CLEAR_DIS, 1, \
+ __func__, __LINE__)
+#define NF10BMAC_RX_INTR_ENABLE(sc)
\
+ NF10BMAC_WRITE_INTR((sc), NF10BMAC_INTR_CTRL, 1, \
+ __func__, __LINE__)
+#define NF10BMAC_RX_INTR_DISABLE(sc)
\
+ NF10BMAC_WRITE_INTR((sc), NF10BMAC_INTR_CTRL, 0, \
+ __func__, __LINE__)
+
+
#ifdef ENABLE_WATCHDOG
static void nf10bmac_tick(void *);
#endif
@@ -178,7 +218,7 @@ static int
nf10bmac_tx_locked(struct nf10bmac_softc *sc, struct mbuf *m)
{
int32_t len, l, ml;
- uint32_t m4, val4;
+ REGWTYPE md, val;
NF10BMAC_LOCK_ASSERT(sc);
@@ -193,16 +233,16 @@ nf10bmac_tx_locked(struct nf10bmac_softc
len = m->m_pkthdr.len;
/* Write the length at start of packet. */
- NF10BMAC_WRITE_4(sc, NF10BMAC_TX_LEN, len);
+ NF10BMAC_WRITE(sc, NF10BMAC_TX_LEN, len);
/* Write the meta data and data. */
- ml = len / sizeof(val4);
- len -= (ml * sizeof(val4));
+ ml = len / sizeof(val);
+ len -= (ml * sizeof(val));
for (l = 0; l <= ml; l++) {
int32_t cl;
- cl = sizeof(val4);
- m4 = (NF10BMAC_TUSER_CPU0 << NF10BMAC_DATA_SPORT_SHIFT);
+ cl = sizeof(val);
+ md = (NF10BMAC_TUSER_CPU0 << NF10BMAC_DATA_SPORT_SHIFT);
if (l == ml || (len == 0 && l == (ml - 1))) {
if (l == ml && len == 0) {
break;
@@ -211,20 +251,20 @@ nf10bmac_tx_locked(struct nf10bmac_softc
int sl;
if (l == (ml - 1))
- len = 4;
+ len = sizeof(val);
cl = len;
for (s = 0, sl = len; sl > 0; sl--)
s |= (1 << (sl - 1));
- m4 |= (s & NF10BMAC_DATA_STRB);
- m4 |= NF10BMAC_DATA_LAST;
+ md |= (s & NF10BMAC_DATA_STRB);
+ md |= NF10BMAC_DATA_LAST;
}
} else {
- m4 |= NF10BMAC_DATA_STRB;
+ md |= NF10BMAC_DATA_STRB;
}
- NF10BMAC_WRITE_4(sc, NF10BMAC_TX_META, m4);
- bcopy(&sc->nf10bmac_tx_buf[l*sizeof(val4)], &val4, cl);
- NF10BMAC_WRITE_4_BE(sc, NF10BMAC_TX_DATA, val4);
+ NF10BMAC_WRITE(sc, NF10BMAC_TX_META, md);
+ bcopy(&sc->nf10bmac_tx_buf[l*sizeof(val)], &val, cl);
+ NF10BMAC_WRITE_BE(sc, NF10BMAC_TX_DATA, val);
}
/* If anyone is interested give them a copy. */
@@ -293,14 +333,14 @@ nf10bmac_start(struct ifnet *ifp)
static void
nf10bmac_eat_packet_munch_munch(struct nf10bmac_softc *sc)
{
- uint32_t m4, val4;
+ REGWTYPE md, val;
do {
- m4 = NF10BMAC_READ_4_BE(sc, NF10BMAC_RX_META);
- if ((m4 & NF10BMAC_DATA_STRB) != 0)
- val4 = NF10BMAC_READ_4_BE(sc, NF10BMAC_RX_DATA);
- } while ((m4 & NF10BMAC_DATA_STRB) != 0 &&
- (m4 & NF10BMAC_DATA_LAST) == 0);
+ md = NF10BMAC_READ_BE(sc, NF10BMAC_RX_META);
+ if ((md & NF10BMAC_DATA_STRB) != 0)
+ val = NF10BMAC_READ_BE(sc, NF10BMAC_RX_DATA);
+ } while ((md & NF10BMAC_DATA_STRB) != 0 &&
+ (md & NF10BMAC_DATA_LAST) == 0);
}
static int
@@ -308,7 +348,7 @@ nf10bmac_rx_locked(struct nf10bmac_softc
{
struct ifnet *ifp;
struct mbuf *m;
- uint32_t m4, val4;
+ REGWTYPE md, val;
int32_t len, l;
/*
@@ -318,21 +358,21 @@ nf10bmac_rx_locked(struct nf10bmac_softc
* skip to tlast).
*/
- len = NF10BMAC_READ_4(sc, NF10BMAC_RX_LEN);
+ len = NF10BMAC_READ(sc, NF10BMAC_RX_LEN) & NF10BMAC_DATA_LEN_MASK;
if (len > (MCLBYTES - ETHER_ALIGN)) {
nf10bmac_eat_packet_munch_munch(sc);
return (0);
}
- m4 = NF10BMAC_READ_4(sc, NF10BMAC_RX_META);
- if (len == 0 && (m4 & NF10BMAC_DATA_STRB) == 0) {
+ md = NF10BMAC_READ(sc, NF10BMAC_RX_META);
+ if (len == 0 && (md & NF10BMAC_DATA_STRB) == 0) {
/* No packet data available. */
return (0);
- } else if (len == 0 && (m4 & NF10BMAC_DATA_STRB) != 0) {
+ } else if (len == 0 && (md & NF10BMAC_DATA_STRB) != 0) {
/* We are in the middle of a packet. */
nf10bmac_eat_packet_munch_munch(sc);
return (0);
- } else if ((m4 & NF10BMAC_DATA_STRB) == 0) {
+ } else if ((md & NF10BMAC_DATA_STRB) == 0) {
/* Invalid length "hint". */
device_printf(sc->nf10bmac_dev,
"Unexpected length %d on zero strb\n", len);
@@ -359,13 +399,13 @@ nf10bmac_rx_locked(struct nf10bmac_softc
ifp = sc->nf10bmac_ifp;
l = 0;
/*
- while ((m4 & NF10BMAC_DATA_STRB) != 0 && l < len) {
+ while ((md & NF10BMAC_DATA_STRB) != 0 && l < len) {
*/
while (l < len) {
size_t cl;
- if ((m4 & NF10BMAC_DATA_LAST) == 0 &&
- (len - l) < sizeof(val4)) {
+ if ((md & NF10BMAC_DATA_LAST) == 0 &&
+ (len - l) < sizeof(val)) {
/*
* Our length and LAST disagree. We have a valid STRB.
* We could continue until we fill the mbuf and just
@@ -376,34 +416,34 @@ nf10bmac_rx_locked(struct nf10bmac_softc
ifp->if_ierrors++;
m_freem(m);
return (0);
- } else if ((len - l) <= sizeof(val4)) {
+ } else if ((len - l) <= sizeof(val)) {
cl = len - l;
} else {
- cl = sizeof(val4);
+ cl = sizeof(val);
}
/* Read the first bytes of data as well. */
- val4 = NF10BMAC_READ_4_BE(sc, NF10BMAC_RX_DATA);
- bcopy(&val4, (uint8_t *)(m->m_data + l), cl);
+ val = NF10BMAC_READ_BE(sc, NF10BMAC_RX_DATA);
+ bcopy(&val, (uint8_t *)(m->m_data + l), cl);
l += cl;
- if ((m4 & NF10BMAC_DATA_LAST) != 0 || l >= len)
+ if ((md & NF10BMAC_DATA_LAST) != 0 || l >= len)
break;
else {
DELAY(50);
- m4 = NF10BMAC_READ_4(sc, NF10BMAC_RX_META);
+ md = NF10BMAC_READ(sc, NF10BMAC_RX_META);
}
cl = 10;
- while ((m4 & NF10BMAC_DATA_STRB) == 0 && cl-- > 0) {
+ while ((md & NF10BMAC_DATA_STRB) == 0 && cl-- > 0) {
DELAY(10);
- m4 = NF10BMAC_READ_4(sc, NF10BMAC_RX_META);
+ md = NF10BMAC_READ(sc, NF10BMAC_RX_META);
}
}
/* We should get out of this loop with tlast and tsrb. */
- if ((m4 & NF10BMAC_DATA_LAST) == 0 || (m4 & NF10BMAC_DATA_STRB) == 0) {
+ if ((md & NF10BMAC_DATA_LAST) == 0 || (md & NF10BMAC_DATA_STRB) == 0) {
device_printf(sc->nf10bmac_dev, "Unexpected rx loop end state: "
- "m4=0x%08x len=%d l=%d\n", m4, len, l);
+ "md=0x%08jx len=%d l=%d\n", (uintmax_t)md, len, l);
ifp->if_ierrors++;
m_freem(m);
return (0);
@@ -435,6 +475,7 @@ nf10bmac_stop_locked(struct nf10bmac_sof
ifp = sc->nf10bmac_ifp;
ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+ NF10BMAC_RX_INTR_CLEAR_DIS(sc);
sc->nf10bmac_flags &= ~NF10BMAC_FLAGS_LINK;
if_link_state_change(ifp, LINK_STATE_DOWN);
@@ -446,7 +487,25 @@ static int
nf10bmac_reset(struct nf10bmac_softc *sc)
{
- /* Currently we cannot do anything. */
+ /*
+ * If we do not have an ether address set, initialize to the same
+ * OUI as NetFPGA-10G Linux driver does (which luckily seems
+ * unallocated). We just change the NIC specific part from
+ * the slightly long "\0NF10C0" to "\0NFBSD".
+ * Oh and we keep the way of setting it from a string as they do.
+ * It's an amazing way to hide it.
+ * XXX-BZ If NetFPGA gets their own OUI we should fix this.
+ */
+ if (sc->nf10bmac_eth_addr[0] == 0x00 &&
+ sc->nf10bmac_eth_addr[1] == 0x00 &&
+ sc->nf10bmac_eth_addr[2] == 0x00 &&
+ sc->nf10bmac_eth_addr[3] == 0x00 &&
+ sc->nf10bmac_eth_addr[4] == 0x00 &&
+ sc->nf10bmac_eth_addr[5] == 0x00) {
+ memcpy(&sc->nf10bmac_eth_addr, "\0NFBSD", ETHER_ADDR_LEN);
+ sc->nf10bmac_eth_addr[5] += sc->nf10bmac_unit;
+ }
+
return (0);
}
@@ -480,6 +539,16 @@ nf10bmac_init_locked(struct nf10bmac_sof
/* Instead drain the FIFO; or at least a possible first packet.. */
nf10bmac_eat_packet_munch_munch(sc);
+#ifdef DEVICE_POLLING
+ /* Only enable interrupts if we are not polling. */
+ if (ifp->if_capenable & IFCAP_POLLING) {
+ NF10BMAC_RX_INTR_CLEAR_DIS(sc);
+ } else
+#endif
+ {
+ NF10BMAC_RX_INTR_ENABLE(sc);
+ }
+
ifp->if_drv_flags |= IFF_DRV_RUNNING;
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
@@ -538,6 +607,49 @@ nf10bmac_tick(void *xsc)
}
#endif
+static void
+nf10bmac_intr(void *arg)
+{
+ struct nf10bmac_softc *sc;
+ struct ifnet *ifp;
+ int rx_npkts;
+
+ sc = (struct nf10bmac_softc *)arg;
+ ifp = sc->nf10bmac_ifp;
+
+ NF10BMAC_LOCK(sc);
+#ifdef DEVICE_POLLING
+ if (ifp->if_capenable & IFCAP_POLLING) {
+ NF10BMAC_UNLOCK(sc);
+ return;
+ }
+#endif
+
+ /* NF10BMAC_RX_INTR_DISABLE(sc); */
+ NF10BMAC_RX_INTR_CLEAR_DIS(sc);
+
+ /* We only have an RX interrupt and no status information. */
+ rx_npkts = 0;
+ while (rx_npkts < NF10BMAC_MAX_PKTS) {
+ int c;
+
+ c = nf10bmac_rx_locked(sc);
+ rx_npkts += c;
+ if (c == 0)
+ break;
+ }
+
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+ /* Re-enable interrupts. */
+ NF10BMAC_RX_INTR_ENABLE(sc);
+
+ if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+ nf10bmac_start_locked(ifp);
+ }
+ NF10BMAC_UNLOCK(sc);
+}
+
+
#ifdef DEVICE_POLLING
static int
nf10bmac_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
@@ -631,10 +743,16 @@ nf10bmac_ioctl(struct ifnet *ifp, u_long
break;
}
+ NF10BMAC_RX_INTR_CLEAR_DIS(sc);
+
/*
* Do not allow disabling of polling if we do
* not have interrupts.
*/
+ } else if (sc->nf10bmac_rx_irq_res != NULL) {
+ error = ether_poll_deregister(ifp);
+ /* Enable interrupts. */
+ NF10BMAC_RX_INTR_ENABLE(sc);
} else {
ifp->if_capenable ^= IFCAP_POLLING;
error = EINVAL;
@@ -655,7 +773,6 @@ nf10bmac_ioctl(struct ifnet *ifp, u_long
return (error);
}
-
/*
* Generic device handling routines.
*/
@@ -715,18 +832,40 @@ nf10bmac_attach(device_t dev)
ifmedia_add(&sc->nf10bmac_media, IFM_ETHER | IFM_10G_T, 0, NULL);
ifmedia_set(&sc->nf10bmac_media, IFM_ETHER | IFM_10G_T);
- /* Interrupts would go here. */
+ /* Initialise. */
+ error = 0;
+
+ /* Hook up interrupts. Well the one. */
+ if (sc->nf10bmac_rx_irq_res != NULL) {
+ error = bus_setup_intr(dev, sc->nf10bmac_rx_irq_res,
+ INTR_TYPE_NET | INTR_MPSAFE, NULL, nf10bmac_intr,
+ sc, &sc->nf10bmac_rx_intrhand);
+ if (error != 0) {
+ device_printf(dev, "enabling RX IRQ failed\n");
+ ether_ifdetach(ifp);
+ goto err;
+ }
+ }
+ if ((ifp->if_capenable & IFCAP_POLLING) != 0 ||
+ sc->nf10bmac_rx_irq_res == NULL) {
#ifdef DEVICE_POLLING
- ifp->if_capenable |= IFCAP_POLLING;
- device_printf(dev, "forcing to polling due to no interrupts\n");
- error = ether_poll_register(nf10bmac_poll, ifp);
- if (error != 0)
- goto err;
+ /* If not on and no IRQs force it on. */
+ if (sc->nf10bmac_rx_irq_res == NULL) {
+ ifp->if_capenable |= IFCAP_POLLING;
+ device_printf(dev,
+ "forcing to polling due to no interrupts\n");
+ }
+ error = ether_poll_register(nf10bmac_poll, ifp);
+ if (error != 0)
+ goto err;
#else
- device_printf(dev, "no DEVICE_POLLING in kernel and no IRQs\n");
- error = ENXIO;
+ device_printf(dev, "no DEVICE_POLLING in kernel and no IRQs\n");
+ error = ENXIO;
#endif
+ } else {
+ NF10BMAC_RX_INTR_ENABLE(sc);
+ }
err:
if (error != 0)
@@ -762,6 +901,10 @@ nf10bmac_detach(device_t dev)
ether_ifdetach(ifp);
}
+ if (sc->nf10bmac_rx_intrhand)
+ bus_teardown_intr(dev, sc->nf10bmac_rx_irq_res,
+ sc->nf10bmac_rx_intrhand);
+
if (ifp != NULL)
if_free(ifp);
ifmedia_removeall(&sc->nf10bmac_media);
@@ -779,10 +922,15 @@ nf10bmac_detach_resources(device_t dev)
sc = device_get_softc(dev);
- if (sc->nf10bmac_mem_res != NULL) {
+ if (sc->nf10bmac_rx_irq_res != NULL) {
+ bus_release_resource(dev, SYS_RES_IRQ, sc->nf10bmac_rx_irq_rid,
+ sc->nf10bmac_rx_irq_res);
+ sc->nf10bmac_rx_irq_res = NULL;
+ }
+ if (sc->nf10bmac_intr_res != NULL) {
bus_release_resource(dev, SYS_RES_MEMORY,
- sc->nf10bmac_mem_rid, sc->nf10bmac_mem_res);
- sc->nf10bmac_mem_res = NULL;
+ sc->nf10bmac_intr_rid, sc->nf10bmac_intr_res);
+ sc->nf10bmac_intr_res = NULL;
}
if (sc->nf10bmac_rx_mem_res != NULL) {
bus_release_resource(dev, SYS_RES_MEMORY,
@@ -794,6 +942,11 @@ nf10bmac_detach_resources(device_t dev)
sc->nf10bmac_tx_mem_rid, sc->nf10bmac_tx_mem_res);
sc->nf10bmac_tx_mem_res = NULL;
}
+ if (sc->nf10bmac_ctrl_res != NULL) {
+ bus_release_resource(dev, SYS_RES_MEMORY,
+ sc->nf10bmac_ctrl_rid, sc->nf10bmac_ctrl_res);
+ sc->nf10bmac_ctrl_res = NULL;
+ }
}
int
Modified: stable/10/sys/dev/netfpga10g/nf10bmac/if_nf10bmac_fdt.c
==============================================================================
--- head/sys/dev/netfpga10g/nf10bmac/if_nf10bmac_fdt.c Thu Apr 17 12:33:26
2014 (r264601)
+++ stable/10/sys/dev/netfpga10g/nf10bmac/if_nf10bmac_fdt.c Sat Aug 16
14:30:46 2014 (r270061)
@@ -85,16 +85,34 @@ nf10bmac_attach_fdt(device_t dev)
/*
* FDT lists our resources. For convenience we use three different
* mappings. We need to attach them in the oder specified in .dts:
- * TX (size 0xc), RX (size 0xc), LOOP (size 0x4).
+ * LOOP (size 0x1f), TX (0x2f), RX (0x2f), INTR (0xf).
*/
+ /*
+ * LOOP memory region (this could be a general control region).
+ * 0x00: 32/64bit register to enable a Y-"lopback".
+ */
+ sc->nf10bmac_ctrl_rid = 0;
+ sc->nf10bmac_ctrl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->nf10bmac_ctrl_rid, RF_ACTIVE);
+ if (sc->nf10bmac_ctrl_res == NULL) {
+ device_printf(dev, "failed to map memory for CTRL region\n");
+ error = ENXIO;
+ goto err;
+ }
+ if (bootverbose)
+ device_printf(sc->nf10bmac_dev, "CTRL region at mem %p-%p\n",
+ (void *)rman_get_start(sc->nf10bmac_ctrl_res),
+ (void *)(rman_get_start(sc->nf10bmac_ctrl_res) +
+ rman_get_size(sc->nf10bmac_ctrl_res)));
+
/*
* TX and TX metadata FIFO memory region.
- * 0x00: 32bit FIFO data,
- * 0x04: 32bit FIFO metadata,
- * 0x08: 32bit packet length.
+ * 0x00: 32/64bit FIFO data,
+ * 0x08: 32/64bit FIFO metadata,
+ * 0x10: 32/64bit packet length.
*/
- sc->nf10bmac_tx_mem_rid = 0;
+ sc->nf10bmac_tx_mem_rid = 1;
sc->nf10bmac_tx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&sc->nf10bmac_tx_mem_rid, RF_ACTIVE);
if (sc->nf10bmac_tx_mem_res == NULL) {
@@ -110,11 +128,11 @@ nf10bmac_attach_fdt(device_t dev)
/*
* RX and RXC metadata FIFO memory region.
- * 0x00: 32bit FIFO data,
- * 0x04: 32bit FIFO metadata,
- * 0x08: 32bit packet length.
+ * 0x00: 32/64bit FIFO data,
+ * 0x08: 32/64bit FIFO metadata,
+ * 0x10: 32/64bit packet length.
*/
- sc->nf10bmac_rx_mem_rid = 1;
+ sc->nf10bmac_rx_mem_rid = 2;
sc->nf10bmac_rx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&sc->nf10bmac_rx_mem_rid, RF_ACTIVE);
if (sc->nf10bmac_rx_mem_res == NULL) {
@@ -129,22 +147,28 @@ nf10bmac_attach_fdt(device_t dev)
rman_get_size(sc->nf10bmac_rx_mem_res)));
/*
- * LOOP memory region (this could be a general control region).
- * 0x00: 32bit register to enable a Y-"lopback".
+ * Interrupt handling registers.
+ * 0x00: 32/64bit register to clear (and disable) the RX interrupt.
+ * 0x08: 32/64bit register to enable or disable the RX interrupt.
*/
- sc->nf10bmac_mem_rid = 2;
- sc->nf10bmac_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
- &sc->nf10bmac_mem_rid, RF_ACTIVE);
- if (sc->nf10bmac_mem_res == NULL) {
- device_printf(dev, "failed to map memory for CTRL region\n");
+ sc->nf10bmac_intr_rid = 3;
+ sc->nf10bmac_intr_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->nf10bmac_intr_rid, RF_ACTIVE);
+ if (sc->nf10bmac_intr_res == NULL) {
+ device_printf(dev, "failed to map memory for INTR region\n");
error = ENXIO;
goto err;
}
if (bootverbose)
- device_printf(sc->nf10bmac_dev, "CTRL region at mem %p-%p\n",
- (void *)rman_get_start(sc->nf10bmac_mem_res),
- (void *)(rman_get_start(sc->nf10bmac_mem_res) +
- rman_get_size(sc->nf10bmac_mem_res)));
+ device_printf(sc->nf10bmac_dev, "INTR region at mem %p-%p\n",
+ (void *)rman_get_start(sc->nf10bmac_intr_res),
+ (void *)(rman_get_start(sc->nf10bmac_intr_res) +
+ rman_get_size(sc->nf10bmac_intr_res)));
+
+ /* (Optional) RX and TX IRQ. */
+ sc->nf10bmac_rx_irq_rid = 0;
+ sc->nf10bmac_rx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+ &sc->nf10bmac_rx_irq_rid, RF_ACTIVE | RF_SHAREABLE);
error = nf10bmac_attach(dev);
if (error)
Modified: stable/10/sys/dev/netfpga10g/nf10bmac/if_nf10bmacreg.h
==============================================================================
--- head/sys/dev/netfpga10g/nf10bmac/if_nf10bmacreg.h Thu Apr 17 12:33:26
2014 (r264601)
+++ stable/10/sys/dev/netfpga10g/nf10bmac/if_nf10bmacreg.h Sat Aug 16
14:30:46 2014 (r270061)
@@ -35,15 +35,20 @@
struct nf10bmac_softc {
struct ifnet *nf10bmac_ifp;
+ struct resource *nf10bmac_ctrl_res;
struct resource *nf10bmac_tx_mem_res;
struct resource *nf10bmac_rx_mem_res;
- struct resource *nf10bmac_mem_res;
+ struct resource *nf10bmac_intr_res;
+ struct resource *nf10bmac_rx_irq_res;
+ void *nf10bmac_rx_intrhand;
uint8_t *nf10bmac_tx_buf;
device_t nf10bmac_dev;
int nf10bmac_unit;
+ int nf10bmac_ctrl_rid;
int nf10bmac_tx_mem_rid;
int nf10bmac_rx_mem_rid;
- int nf10bmac_mem_rid;
+ int nf10bmac_intr_rid;
+ int nf10bmac_rx_irq_rid;
int nf10bmac_if_flags;
uint32_t nf10bmac_flags;
#define NF10BMAC_FLAGS_LINK 0x00000001
Modified: stable/10/sys/mips/beri/files.beri
==============================================================================
--- stable/10/sys/mips/beri/files.beri Sat Aug 16 14:21:03 2014
(r270060)
+++ stable/10/sys/mips/beri/files.beri Sat Aug 16 14:30:46 2014
(r270061)
@@ -6,6 +6,8 @@ dev/altera/jtag_uart/altera_jtag_uart_co
dev/altera/jtag_uart/altera_jtag_uart_tty.c optional altera_jtag_uart
dev/altera/jtag_uart/altera_jtag_uart_fdt.c optional altera_jtag_uart fdt
dev/altera/jtag_uart/altera_jtag_uart_nexus.c optional altera_jtag_uart
+dev/netfpga10g/nf10bmac/if_nf10bmac_fdt.c optional netfpga10g_nf10bmac fdt
+dev/netfpga10g/nf10bmac/if_nf10bmac.c optional netfpga10g_nf10bmac
dev/terasic/de4led/terasic_de4led.c optional terasic_de4led
dev/terasic/de4led/terasic_de4led_fdt.c optional terasic_de4led fdt
dev/terasic/de4led/terasic_de4led_nexus.c optional terasic_de4led
Modified: stable/10/sys/mips/conf/BERI_NETFPGA_MDROOT
==============================================================================
--- stable/10/sys/mips/conf/BERI_NETFPGA_MDROOT Sat Aug 16 14:21:03 2014
(r270060)
+++ stable/10/sys/mips/conf/BERI_NETFPGA_MDROOT Sat Aug 16 14:30:46 2014
(r270061)
@@ -19,6 +19,11 @@ makeoptions FDT_DTS_FILE=beri-netfpga.dt
#device uart
device altera_jtag_uart
+device bpf
+
+options DEVICE_POLLING
+device netfpga10g_nf10bmac
+
#
# This kernel configuration uses an embedded memory root file system.
# Adjust the following path and size based on local requirements.
Modified: stable/10/sys/modules/Makefile
==============================================================================
--- stable/10/sys/modules/Makefile Sat Aug 16 14:21:03 2014
(r270060)
+++ stable/10/sys/modules/Makefile Sat Aug 16 14:30:46 2014
(r270061)
@@ -239,6 +239,7 @@ SUBDIR= \
${_ncp} \
${_ncv} \
${_ndis} \
+ netfpga10g \
${_netgraph} \
${_nfe} \
nfs_common \
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