Author: sgalabov
Date: Tue May 17 06:30:46 2016
New Revision: 300012
URL: https://svnweb.freebsd.org/changeset/base/300012

Log:
  Fix issues with mt762x etherswitch driver
  
  Fix issues that crept in with initial import.
  
  Approved by:  adrian (mentor)
  Sponsored by: Smartcom - Bulgaria AD
  Differential Revision:        https://reviews.freebsd.org/D6393

Modified:
  head/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c
  head/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.h

Modified: head/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c
==============================================================================
--- head/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c       Tue May 17 
06:28:03 2016        (r300011)
+++ head/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c       Tue May 17 
06:30:46 2016        (r300012)
@@ -119,7 +119,6 @@ static uint32_t
 mtkswitch_reg_read32(struct mtkswitch_softc *sc, int reg)
 {
 
-       MTKSWITCH_LOCK_ASSERT(sc, MA_OWNED);
        return (MTKSWITCH_READ(sc, reg));
 }
 
@@ -127,7 +126,6 @@ static uint32_t
 mtkswitch_reg_write32(struct mtkswitch_softc *sc, int reg, uint32_t val)
 {
 
-       MTKSWITCH_LOCK_ASSERT(sc, MA_OWNED);
        MTKSWITCH_WRITE(sc, reg, val);
        return (0);
 }
@@ -230,15 +228,21 @@ mtkswitch_port_init(struct mtkswitch_sof
        /* Called early and hence unlocked */
 
        /* Set the port to secure mode */
-       sc->hal.mtkswitch_write(sc, MTKSWITCH_PCR(port), PCR_PORT_VLAN_SECURE);
+       val = sc->hal.mtkswitch_read(sc, MTKSWITCH_PCR(port));
+       val |= PCR_PORT_VLAN_SECURE;
+       sc->hal.mtkswitch_write(sc, MTKSWITCH_PCR(port), val);
 
        /* Set port's vlan_attr to user port */
        val = sc->hal.mtkswitch_read(sc, MTKSWITCH_PVC(port));
-       val &= PVC_VLAN_ATTR_MASK;
+       val &= ~PVC_VLAN_ATTR_MASK;
        sc->hal.mtkswitch_write(sc, MTKSWITCH_PVC(port), val);
 
+       val = PMCR_CFG_DEFAULT;
+       if (port == sc->cpuport)
+               val |= PMCR_FORCE_LINK | PMCR_FORCE_DPX | PMCR_FORCE_SPD_1000 |
+                   PMCR_FORCE_MODE;
        /* Set port's MAC to default settings */
-       sc->hal.mtkswitch_write(sc, MTKSWITCH_PMCR(port), PMCR_CFG_DEFAULT);
+       sc->hal.mtkswitch_write(sc, MTKSWITCH_PMCR(port), val);
 }
 
 static uint32_t
@@ -353,13 +357,12 @@ mtkswitch_vlan_init_hw(struct mtkswitch_
 
        MTKSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
        MTKSWITCH_LOCK(sc);
-
        /* Reset all VLANs to defaults first */
        for (i = 0; i < sc->info.es_nvlangroups; i++) {
                mtkswitch_invalidate_vlan(sc, i);
                if (sc->sc_switchtype == MTK_SWITCH_MT7620) {
                        val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VTIM(i));
-                       val &= (VTIM_MASK << VTIM_OFF(i));
+                       val &= ~(VTIM_MASK << VTIM_OFF(i));
                        val |= ((i + 1) << VTIM_OFF(i));
                        sc->hal.mtkswitch_write(sc, MTKSWITCH_VTIM(i), val);
                }
@@ -464,7 +467,7 @@ mtkswitch_vlan_setvgroup(struct mtkswitc
        if (sc->sc_switchtype == MTK_SWITCH_MT7620) {
                val = sc->hal.mtkswitch_read(sc,
                    MTKSWITCH_VTIM(v->es_vlangroup));
-               val &= (VTIM_MASK << VTIM_OFF(v->es_vlangroup));
+               val &= ~(VTIM_MASK << VTIM_OFF(v->es_vlangroup));
                val |= ((v->es_vid & VTIM_MASK) << VTIM_OFF(v->es_vlangroup));
                sc->hal.mtkswitch_write(sc, MTKSWITCH_VTIM(v->es_vlangroup),
                    val);

Modified: head/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.h
==============================================================================
--- head/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.h       Tue May 17 
06:28:03 2016        (r300011)
+++ head/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.h       Tue May 17 
06:30:46 2016        (r300012)
@@ -85,13 +85,21 @@
 #define                PPBV_VID_MASK           0xfff
 
 #define        MTKSWITCH_PMCR(x)       MTKSWITCH_PORTREG(0x3000, (x))
+#define                PMCR_FORCE_LINK         (1u<<0)
+#define                PMCR_FORCE_DPX          (1u<<1)
+#define                PMCR_FORCE_SPD_1000     (2u<<2)
+#define                PMCR_FORCE_TX_FC        (1u<<4)
+#define                PMCR_FORCE_RX_FC        (1u<<5)
 #define                PMCR_BACKPR_EN          (1u<<8)
 #define                PMCR_BKOFF_EN           (1u<<9)
 #define                PMCR_MAC_RX_EN          (1u<<13)
 #define                PMCR_MAC_TX_EN          (1u<<14)
+#define                PMCR_FORCE_MODE         (1u<<15)
+#define                PMCR_RES_1              (1u<<16)
 #define                PMCR_IPG_CFG_RND        (1u<<18)
 #define                PMCR_CFG_DEFAULT        (PMCR_BACKPR_EN | PMCR_BKOFF_EN 
| \
-                   PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_IPG_CFG_RND)
+                   PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_IPG_CFG_RND |  \
+                   PMCR_FORCE_RX_FC | PMCR_FORCE_TX_FC | PMCR_RES_1)
 
 #define        MTKSWITCH_PMSR(x)       MTKSWITCH_PORTREG(0x3008, (x))
 #define                PMSR_MAC_LINK_STS       (1u<<0)
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