Author: jmcneill
Date: Wed Jul 13 20:44:02 2016
New Revision: 302785
URL: https://svnweb.freebsd.org/changeset/base/302785
Log:
H3/A83T: Use PLL_PERIPH/2 for AHB2 parent clock.
Reviewed by: manu
Modified:
head/sys/arm/allwinner/clk/aw_ahbclk.c
Modified: head/sys/arm/allwinner/clk/aw_ahbclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_ahbclk.c Wed Jul 13 19:41:19 2016
(r302784)
+++ head/sys/arm/allwinner/clk/aw_ahbclk.c Wed Jul 13 20:44:02 2016
(r302785)
@@ -140,10 +140,14 @@ aw_ahbclk_init(struct clknode *clk, devi
A83T_AHB1_CLK_SRC_SEL_SHIFT;
break;
case AW_H3_AHB2:
+ /* Set source to PLL_PERIPH/2 */
+ index = H3_AHB2_CLK_CFG_PLL_PERIPH_DIV2;
DEVICE_LOCK(sc);
AHBCLK_READ(sc, &val);
+ val &= ~H3_AHB2_CLK_CFG;
+ val |= (index << H3_AHB2_CLK_CFG_SHIFT);
+ AHBCLK_WRITE(sc, val);
DEVICE_UNLOCK(sc);
- index = (val & H3_AHB2_CLK_CFG) >> H3_AHB2_CLK_CFG_SHIFT;
break;
default:
return (ENXIO);
@@ -189,12 +193,7 @@ aw_ahbclk_recalc_freq(struct clknode *cl
pre_div = 1;
break;
case AW_H3_AHB2:
- src_sel = (val & H3_AHB2_CLK_CFG) >> H3_AHB2_CLK_CFG_SHIFT;
- if (src_sel == H3_AHB2_CLK_CFG_PLL_PERIPH_DIV2)
- div = 2;
- else
- div = 1;
- pre_div = 1;
+ div = pre_div = 1;
break;
default:
div = 1 << ((val & A10_AHB_CLK_DIV_RATIO) >>
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