Author: dim
Date: Wed Jan  4 22:25:16 2017
New Revision: 311328
URL: https://svnweb.freebsd.org/changeset/base/311328

Log:
  Vendor import of llvm trunk r291015:
  https://llvm.org/svn/llvm-project/llvm/trunk@291015

Added:
  vendor/llvm/dist/test/CodeGen/PowerPC/fp64-to-int16.ll
Modified:
  vendor/llvm/dist/include/llvm/Support/FileSystem.h
  vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  vendor/llvm/dist/test/CodeGen/AArch64/fptouint-i8-zext.ll

Modified: vendor/llvm/dist/include/llvm/Support/FileSystem.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Support/FileSystem.h  Wed Jan  4 22:19:42 
2017        (r311327)
+++ vendor/llvm/dist/include/llvm/Support/FileSystem.h  Wed Jan  4 22:25:16 
2017        (r311328)
@@ -858,7 +858,7 @@ public:
 
   // No operator++ because we need error_code.
   recursive_directory_iterator &increment(std::error_code &ec) {
-    const directory_iterator end_itr;
+    const directory_iterator end_itr = {};
 
     if (State->HasNoPushRequest)
       State->HasNoPushRequest = false;
@@ -905,7 +905,7 @@ public:
     assert(State && "Cannot pop an end iterator!");
     assert(State->Level > 0 && "Cannot pop an iterator with level < 1");
 
-    const directory_iterator end_itr;
+    const directory_iterator end_itr = {};
     std::error_code ec;
     do {
       if (ec)

Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp  Wed Jan 
 4 22:19:42 2017        (r311327)
+++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp  Wed Jan 
 4 22:25:16 2017        (r311328)
@@ -428,7 +428,11 @@ SDValue DAGTypeLegalizer::PromoteIntRes_
   // Assert that the converted value fits in the original type.  If it doesn't
   // (eg: because the value being converted is too big), then the result of the
   // original operation was undefined anyway, so the assert is still correct.
-  return DAG.getNode(NewOpc == ISD::FP_TO_UINT ?
+  //
+  // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For 
example:
+  //   before legalization: fp-to-uint16, 65534. -> 0xfffe
+  //   after legalization: fp-to-sint32, 65534. -> 0x0000fffe
+  return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
                      ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
                      DAG.getValueType(N->getValueType(0).getScalarType()));
 }

Modified: vendor/llvm/dist/test/CodeGen/AArch64/fptouint-i8-zext.ll
==============================================================================
--- vendor/llvm/dist/test/CodeGen/AArch64/fptouint-i8-zext.ll   Wed Jan  4 
22:19:42 2017        (r311327)
+++ vendor/llvm/dist/test/CodeGen/AArch64/fptouint-i8-zext.ll   Wed Jan  4 
22:25:16 2017        (r311328)
@@ -3,9 +3,11 @@
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64"
 
+; If the float value is negative or too large, the result is undefined anyway;
+; otherwise, fcvtzs must returns a value in [0, 256), which guarantees zext.
+
 ; CHECK-LABEL: float_char_int_func:
 ; CHECK: fcvtzs [[A:w[0-9]+]], s0
-; CHECK-NEXT: and w0, [[A]], #0xff
 ; CHECK-NEXT: ret
 define i32 @float_char_int_func(float %infloatVal) {
 entry:

Added: vendor/llvm/dist/test/CodeGen/PowerPC/fp64-to-int16.ll
==============================================================================
--- /dev/null   00:00:00 1970   (empty, because file is newly added)
+++ vendor/llvm/dist/test/CodeGen/PowerPC/fp64-to-int16.ll      Wed Jan  4 
22:25:16 2017        (r311328)
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 < %s | FileCheck %s
+target triple = "powerpc64le--linux-gnu"
+
+define i1 @Test(double %a) {
+; CHECK-LABEL: Test:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xscvdpsxws 1, 1
+; CHECK-NEXT:    mfvsrwz 3, 1
+; CHECK-NEXT:    xori 3, 3, 65534
+; CHECK-NEXT:    cntlzw 3, 3
+; CHECK-NEXT:    srwi 3, 3, 5
+; CHECK-NEXT:    # implicit-def: %X4
+; CHECK-NEXT:    mr 4, 3
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    blr
+entry:
+  %conv = fptoui double %a to i16
+  %cmp = icmp eq i16 %conv, -2
+  ret i1 %cmp
+}
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