Author: marius
Date: Wed Jul 12 21:46:16 2017
New Revision: 320922
URL: https://svnweb.freebsd.org/changeset/base/320922
Log:
MF11: r320898; MFC: r320577, r320620
Retry up to 2 ms to enable bus power as at least with some Intel
SDHCI/eMMC controllers the first attempt after a D3 to D0 transition,
i. e. when the firmware has put the devices into D3 state before,
can fail.
Approved by: re (gjb)
Modified:
releng/11.1/sys/dev/sdhci/sdhci.c
Directory Properties:
releng/11.1/ (props changed)
Modified: releng/11.1/sys/dev/sdhci/sdhci.c
==============================================================================
--- releng/11.1/sys/dev/sdhci/sdhci.c Wed Jul 12 20:10:53 2017
(r320921)
+++ releng/11.1/sys/dev/sdhci/sdhci.c Wed Jul 12 21:46:16 2017
(r320922)
@@ -366,6 +366,7 @@ sdhci_set_clock(struct sdhci_slot *slot, uint32_t cloc
static void
sdhci_set_power(struct sdhci_slot *slot, u_char power)
{
+ int i;
uint8_t pwr;
if (slot->power == power)
@@ -394,9 +395,20 @@ sdhci_set_power(struct sdhci_slot *slot, u_char power)
break;
}
WR1(slot, SDHCI_POWER_CONTROL, pwr);
- /* Turn on the power. */
+ /*
+ * Turn on VDD1 power. Note that at least some Intel controllers can
+ * fail to enable bus power on the first try after transiting from D3
+ * to D0, so we give them up to 2 ms.
+ */
pwr |= SDHCI_POWER_ON;
- WR1(slot, SDHCI_POWER_CONTROL, pwr);
+ for (i = 0; i < 20; i++) {
+ WR1(slot, SDHCI_POWER_CONTROL, pwr);
+ if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
+ break;
+ DELAY(100);
+ }
+ if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
+ slot_printf(slot, "Bus power failed to enable");
if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
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