Author: manu
Date: Fri Oct 25 18:08:25 2019
New Revision: 354087
URL: https://svnweb.freebsd.org/changeset/base/354087
Log:
arm64: rk3399: Add clock and gate for usb3 clocks
MFC after: 1 month
Modified:
head/sys/arm64/rockchip/clk/rk3399_cru.c
Modified: head/sys/arm64/rockchip/clk/rk3399_cru.c
==============================================================================
--- head/sys/arm64/rockchip/clk/rk3399_cru.c Fri Oct 25 17:56:24 2019
(r354086)
+++ head/sys/arm64/rockchip/clk/rk3399_cru.c Fri Oct 25 18:08:25 2019
(r354087)
@@ -54,9 +54,18 @@ __FBSDID("$FreeBSD$");
#define SCLK_USB2PHY0_REF 123
#define SCLK_USB2PHY1_REF 124
+#define SCLK_USB3OTG0_REF 129
+#define SCLK_USB3OTG1_REF 130
+#define SCLK_USB3OTG0_SUSPEND 131
+#define SCLK_USB3OTG1_SUSPEND 132
#define ACLK_EMMC_CORE 241
#define ACLK_EMMC_NOC 242
#define ACLK_EMMC_GRF 243
+#define ACLK_USB3_NOC 245
+#define ACLK_USB3OTG0 246
+#define ACLK_USB3OTG1 247
+#define ACLK_USB3_RKSOC_AXI_PERF 248
+#define ACLK_USB3_GRF 249
#define PCLK_GPIO2 336
#define PCLK_GPIO3 337
#define PCLK_GPIO4 338
@@ -103,6 +112,12 @@ static struct rk_cru_gate rk3399_gates[] = {
CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1)
CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0)
+ /* CRU_CLKGATE_CON12 */
+ CRU_GATE(SCLK_USB3OTG0_REF, "sclk_usb3otg0_ref", "xin24m", 0x330, 1)
+ CRU_GATE(SCLK_USB3OTG1_REF, "sclk_usb3otg1_ref", "xin24m", 0x330, 2)
+ CRU_GATE(SCLK_USB3OTG0_SUSPEND, "sclk_usb3otg0_suspend", "xin24m",
0x330, 3)
+ CRU_GATE(SCLK_USB3OTG1_SUSPEND, "sclk_usb3otg1_suspend", "xin24m",
0x330, 4)
+
/* CRU_CLKGATE_CON20 */
CRU_GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0x350, 5)
CRU_GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0x350, 6)
@@ -117,6 +132,13 @@ static struct rk_cru_gate rk3399_gates[] = {
CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9)
CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10)
+ /* CRU_CLKGATE_CON30 */
+ CRU_GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", 0x378, 0)
+ CRU_GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0x378, 1)
+ CRU_GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0x378, 2)
+ CRU_GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf",
"aclk_usb3", 0x378, 3)
+ CRU_GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0x378, 4)
+
/* CRU_CLKGATE_CON31 */
CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3)
CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4)
@@ -1066,6 +1088,32 @@ static struct rk_clk_composite_def pclk_perilp1 = {
.flags = RK_CLK_COMPOSITE_HAVE_GATE,
};
+/* USB3 clock */
+
+#define ACLK_USB3 244
+static const char *aclk_usb3_parents[] = {"cpll", "gpll", "npll", "npll"};
+static struct rk_clk_composite_def aclk_usb3 = {
+ .clkdef = {
+ .id = ACLK_USB3,
+ .name = "aclk_usb3",
+ .parent_names = aclk_usb3_parents,
+ .parent_cnt = nitems(aclk_usb3_parents),
+ },
+ /* CRU_CLKSET_CON39 */
+ .muxdiv_offset = 0x19C,
+ .mux_shift = 6,
+ .mux_width = 2,
+
+ .div_shift = 0,
+ .div_width = 5,
+
+ /* CRU_CLKGATE_CON12 */
+ .gate_offset = 0x330,
+ .gate_shift = 0,
+
+ .flags = RK_CLK_COMPOSITE_HAVE_GATE,
+};
+
/*
* i2c
*/
@@ -1210,6 +1258,114 @@ static struct rk_clk_composite_def i2c7 = {
.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
};
+/* USB3 */
+
+#define SCLK_UPHY0_TCPDPHY_REF 125
+#define SCLK_UPHY0_TCPDCORE 126
+
+/* Missing xin32k exported by rk808 */
+static const char *uphy0_tcpdphy_ref_parents[] = {"xin24m"};
+
+static struct rk_clk_composite_def uphy0_tcpdphy_ref = {
+ .clkdef = {
+ .id = SCLK_UPHY0_TCPDPHY_REF,
+ .name = "uphy0_tcpdphy_ref",
+ .parent_names = uphy0_tcpdphy_ref_parents,
+ .parent_cnt = nitems(uphy0_tcpdphy_ref_parents),
+ },
+ /* CRU_CLKSET_CON64 */
+ .muxdiv_offset = 0x0200,
+ .mux_shift = 15,
+ .mux_width = 1,
+
+ .div_shift = 8,
+ .div_width = 5,
+
+ /* CRU_CLKGATE_CON13 */
+ .gate_offset = 0x0334,
+ .gate_shift = 4,
+
+ .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
+};
+
+/* Missing xin32k exported by rk808 */
+static const char *uphy0_tcpdcore_parents[] = {"xin24m", "xin24m", "cpll",
"gpll"};
+
+static struct rk_clk_composite_def uphy0_tcpdcore = {
+ .clkdef = {
+ .id = SCLK_UPHY0_TCPDCORE,
+ .name = "uphy0_tcpdcore",
+ .parent_names = uphy0_tcpdcore_parents,
+ .parent_cnt = nitems(uphy0_tcpdcore_parents),
+ },
+ /* CRU_CLKSET_CON64 */
+ .muxdiv_offset = 0x0200,
+ .mux_shift = 6,
+ .mux_width = 2,
+
+ .div_shift = 0,
+ .div_width = 5,
+
+ /* CRU_CLKGATE_CON13 */
+ .gate_offset = 0x0334,
+ .gate_shift = 5,
+
+ .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
+};
+
+#define SCLK_UPHY1_TCPDPHY_REF 127
+#define SCLK_UPHY1_TCPDCORE 128
+
+/* Missing xin32k exported by rk808 */
+static const char *uphy1_tcpdphy_ref_parents[] = {"xin24m"};
+
+static struct rk_clk_composite_def uphy1_tcpdphy_ref = {
+ .clkdef = {
+ .id = SCLK_UPHY1_TCPDPHY_REF,
+ .name = "uphy1_tcpdphy_ref",
+ .parent_names = uphy1_tcpdphy_ref_parents,
+ .parent_cnt = nitems(uphy1_tcpdphy_ref_parents),
+ },
+ /* CRU_CLKSET_CON65 */
+ .muxdiv_offset = 0x0204,
+ .mux_shift = 15,
+ .mux_width = 1,
+
+ .div_shift = 8,
+ .div_width = 5,
+
+ /* CRU_CLKGATE_CON13 */
+ .gate_offset = 0x0334,
+ .gate_shift = 6,
+
+ .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
+};
+
+/* Missing xin32k exported by rk808 */
+static const char *uphy1_tcpdcore_parents[] = {"xin24m", "xin24m", "cpll",
"gpll"};
+
+static struct rk_clk_composite_def uphy1_tcpdcore = {
+ .clkdef = {
+ .id = SCLK_UPHY1_TCPDCORE,
+ .name = "uphy1_tcpdcore",
+ .parent_names = uphy1_tcpdcore_parents,
+ .parent_cnt = nitems(uphy1_tcpdcore_parents),
+ },
+ /* CRU_CLKSET_CON65 */
+ .muxdiv_offset = 0x0204,
+ .mux_shift = 6,
+ .mux_width = 2,
+
+ .div_shift = 0,
+ .div_width = 5,
+
+ /* CRU_CLKGATE_CON13 */
+ .gate_offset = 0x0334,
+ .gate_shift = 7,
+
+ .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
+};
+
/*
* ARM CPU clocks (LITTLE and big)
*/
@@ -1593,6 +1749,10 @@ static struct rk_clk rk3399_clks[] = {
},
{
.type = RK_CLK_COMPOSITE,
+ .clk.composite = &aclk_usb3,
+ },
+ {
+ .type = RK_CLK_COMPOSITE,
.clk.composite = &i2c1,
},
{
@@ -1614,6 +1774,22 @@ static struct rk_clk rk3399_clks[] = {
{
.type = RK_CLK_COMPOSITE,
.clk.composite = &i2c7,
+ },
+ {
+ .type = RK_CLK_COMPOSITE,
+ .clk.composite = &uphy0_tcpdphy_ref,
+ },
+ {
+ .type = RK_CLK_COMPOSITE,
+ .clk.composite = &uphy0_tcpdcore,
+ },
+ {
+ .type = RK_CLK_COMPOSITE,
+ .clk.composite = &uphy1_tcpdphy_ref,
+ },
+ {
+ .type = RK_CLK_COMPOSITE,
+ .clk.composite = &uphy1_tcpdcore,
},
{
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