Author: dim Date: Fri Jan 2 14:55:02 2015 New Revision: 276537 URL: https://svnweb.freebsd.org/changeset/base/276537
Log: Pull in r222587 from upstream llvm trunk (by Jörg Sonnenberger): Fix transformation of add with pc argument to adr for non-immediate arguments. This fixes an "Unimplemented" error when assembling certain ARM add instructions with pc-relative arguments. Reported by: sbruno PR: 196412, 196423 Modified: head/contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: head/contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp ============================================================================== --- head/contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Jan 2 14:05:30 2015 (r276536) +++ head/contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Jan 2 14:55:02 2015 (r276537) @@ -314,7 +314,7 @@ class ARMAsmParser : public MCTargetAsmP void cvtThumbBranches(MCInst &Inst, const OperandVector &); bool validateInstruction(MCInst &Inst, const OperandVector &Ops); - bool processInstruction(MCInst &Inst, const OperandVector &Ops); + bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out); bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands); bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands); @@ -6175,7 +6175,8 @@ static unsigned getRealVLDOpcode(unsigne } bool ARMAsmParser::processInstruction(MCInst &Inst, - const OperandVector &Operands) { + const OperandVector &Operands, + MCStreamer &Out) { switch (Inst.getOpcode()) { // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction. case ARM::LDRT_POST: @@ -6216,12 +6217,31 @@ bool ARMAsmParser::processInstruction(MC // Alias for alternate form of 'ADR Rd, #imm' instruction. case ARM::ADDri: { if (Inst.getOperand(1).getReg() != ARM::PC || - Inst.getOperand(5).getReg() != 0) + Inst.getOperand(5).getReg() != 0 || + !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) return false; MCInst TmpInst; TmpInst.setOpcode(ARM::ADR); TmpInst.addOperand(Inst.getOperand(0)); - TmpInst.addOperand(Inst.getOperand(2)); + if (Inst.getOperand(2).isImm()) { + TmpInst.addOperand(Inst.getOperand(2)); + } else { + // Turn PC-relative expression into absolute expression. + // Reading PC provides the start of the current instruction + 8 and + // the transform to adr is biased by that. + MCSymbol *Dot = getContext().CreateTempSymbol(); + Out.EmitLabel(Dot); + const MCExpr *OpExpr = Inst.getOperand(2).getExpr(); + const MCExpr *InstPC = MCSymbolRefExpr::Create(Dot, + MCSymbolRefExpr::VK_None, + getContext()); + const MCExpr *Const8 = MCConstantExpr::Create(8, getContext()); + const MCExpr *ReadPC = MCBinaryExpr::CreateAdd(InstPC, Const8, + getContext()); + const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr, + getContext()); + TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr)); + } TmpInst.addOperand(Inst.getOperand(3)); TmpInst.addOperand(Inst.getOperand(4)); Inst = TmpInst; @@ -8061,7 +8081,7 @@ bool ARMAsmParser::MatchAndEmitInstructi // encoding is selected. Loop on it while changes happen so the // individual transformations can chain off each other. E.g., // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) - while (processInstruction(Inst, Operands)) + while (processInstruction(Inst, Operands, Out)) ; // Only after the instruction is fully processed, we can validate it _______________________________________________ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"