Author: andrew
Date: Tue Mar 3 09:48:19 2015
New Revision: 279561
URL: https://svnweb.freebsd.org/changeset/base/279561
Log:
Fix the pl011 driver to work when the uart will write in zero cycles. This
is the case, depending on the options, in some of the ARM hardware
simulators. In these cases we don't get an interrupt so will need to
schedule the task to write more data to the uart.
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Modified:
head/sys/dev/uart/uart_dev_pl011.c
Modified: head/sys/dev/uart/uart_dev_pl011.c
==============================================================================
--- head/sys/dev/uart/uart_dev_pl011.c Tue Mar 3 07:51:36 2015
(r279560)
+++ head/sys/dev/uart/uart_dev_pl011.c Tue Mar 3 09:48:19 2015
(r279561)
@@ -452,15 +452,23 @@ uart_pl011_bus_transmit(struct uart_soft
__uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);
uart_barrier(bas);
}
- sc->sc_txbusy = 1;
- /* Enable TX interrupt */
- reg = __uart_getreg(bas, UART_IMSC);
- reg |= (UART_TXEMPTY);
- __uart_setreg(bas, UART_IMSC, reg);
+ /* If not empty wait until it is */
+ if ((__uart_getreg(bas, UART_FR) & FR_TXFE) != FR_TXFE) {
+ sc->sc_txbusy = 1;
+
+ /* Enable TX interrupt */
+ reg = __uart_getreg(bas, UART_IMSC);
+ reg |= (UART_TXEMPTY);
+ __uart_setreg(bas, UART_IMSC, reg);
+ }
uart_unlock(sc->sc_hwmtx);
+ /* No interrupt expected, schedule the next fifo write */
+ if (!sc->sc_txbusy)
+ uart_sched_softih(sc, SER_INT_TXIDLE);
+
return (0);
}
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