Author: br
Date: Tue Aug 2 14:50:14 2016
New Revision: 303660
URL: https://svnweb.freebsd.org/changeset/base/303660
Log:
Update RISC-V port to Privileged Architecture Version 1.9.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Modified:
head/sys/boot/fdt/dts/riscv/spike.dts
head/sys/cddl/contrib/opensolaris/uts/common/sys/dtrace.h
head/sys/cddl/dev/dtrace/riscv/dtrace_asm.S
head/sys/cddl/dev/dtrace/riscv/dtrace_subr.c
head/sys/conf/ldscript.riscv
head/sys/riscv/conf/GENERIC
head/sys/riscv/htif/htif.c
head/sys/riscv/htif/htif_block.c
head/sys/riscv/htif/htif_console.c
head/sys/riscv/include/cpu.h
head/sys/riscv/include/cpufunc.h
head/sys/riscv/include/db_machdep.h
head/sys/riscv/include/intr.h
head/sys/riscv/include/pte.h
head/sys/riscv/include/riscvreg.h
head/sys/riscv/include/vmparam.h
head/sys/riscv/riscv/exception.S
head/sys/riscv/riscv/genassym.c
head/sys/riscv/riscv/identcpu.c
head/sys/riscv/riscv/intr_machdep.c
head/sys/riscv/riscv/locore.S
head/sys/riscv/riscv/machdep.c
head/sys/riscv/riscv/pmap.c
head/sys/riscv/riscv/swtch.S
head/sys/riscv/riscv/timer.c
head/sys/riscv/riscv/trap.c
head/sys/riscv/riscv/vm_machdep.c
Modified: head/sys/boot/fdt/dts/riscv/spike.dts
==============================================================================
--- head/sys/boot/fdt/dts/riscv/spike.dts Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/boot/fdt/dts/riscv/spike.dts Tue Aug 2 14:50:14 2016
(r303660)
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2015 Ruslan Bukin <b...@bsdpad.com>
+ * Copyright (c) 2015-2016 Ruslan Bukin <b...@bsdpad.com>
* All rights reserved.
*
* Portions of this software were developed by SRI International and the
@@ -37,8 +37,8 @@
/dts-v1/;
/ {
- model = "UC Berkeley Spike Simulator RV64I";
- compatible = "riscv,rv64i";
+ model = "UC Berkeley Spike Simulator RV64";
+ compatible = "riscv,rv64";
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <1>;
@@ -49,14 +49,14 @@
cpu@0 {
device_type = "cpu";
- compatible = "riscv,rv64i";
- reg = <0x40002000>;
+ compatible = "riscv,rv64";
+ reg = <0x40001000>;
};
cpu@1 {
device_type = "cpu";
- compatible = "riscv,rv64i";
- reg = <0x4000a000>;
+ compatible = "riscv,rv64";
+ reg = <0x40002000>;
};
};
@@ -66,12 +66,12 @@
memory {
device_type = "memory";
- reg = <0x0 0x40000000>; /* 1GB at 0x0 */
+ reg = <0x80000000 0x40000000>; /* 1GB at 0x80000000 */
};
soc {
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
#interrupt-cells = <1>;
compatible = "simple-bus";
@@ -84,14 +84,15 @@
timer0: timer@0 {
compatible = "riscv,timer";
- interrupts = < 1 >;
+ reg = < 0x40000000 0x100 >;
+ interrupts = < 5 >;
interrupt-parent = < &pic0 >;
clock-frequency = < 1000000 >;
};
htif0: htif@0 {
compatible = "riscv,htif";
- interrupts = < 0 >;
+ interrupts = < 1 >;
interrupt-parent = < &pic0 >;
console0: console@0 {
Modified: head/sys/cddl/contrib/opensolaris/uts/common/sys/dtrace.h
==============================================================================
--- head/sys/cddl/contrib/opensolaris/uts/common/sys/dtrace.h Tue Aug 2
14:14:36 2016 (r303659)
+++ head/sys/cddl/contrib/opensolaris/uts/common/sys/dtrace.h Tue Aug 2
14:50:14 2016 (r303660)
@@ -2498,8 +2498,8 @@ extern void dtrace_helpers_destroy(proc_
#elif defined(__riscv__)
-#define SD_RA_SP_MASK 0x1fff07f
-#define SD_RA_SP 0x0113023
+#define SD_RA_SP_MASK 0x01fff07f
+#define SD_RA_SP 0x00113023
#define DTRACE_INVOP_SD 1
#define DTRACE_INVOP_RET 2
Modified: head/sys/cddl/dev/dtrace/riscv/dtrace_asm.S
==============================================================================
--- head/sys/cddl/dev/dtrace/riscv/dtrace_asm.S Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/cddl/dev/dtrace/riscv/dtrace_asm.S Tue Aug 2 14:50:14 2016
(r303660)
@@ -57,8 +57,8 @@ END(dtrace_membar_consumer)
dtrace_icookie_t dtrace_interrupt_disable(void)
*/
ENTRY(dtrace_interrupt_disable)
- csrrci a0, sstatus, SSTATUS_IE
- andi a0, a0, SSTATUS_IE
+ csrrci a0, sstatus, (SSTATUS_SIE)
+ andi a0, a0, (SSTATUS_SIE)
RET
END(dtrace_interrupt_disable)
Modified: head/sys/cddl/dev/dtrace/riscv/dtrace_subr.c
==============================================================================
--- head/sys/cddl/dev/dtrace/riscv/dtrace_subr.c Tue Aug 2 14:14:36
2016 (r303659)
+++ head/sys/cddl/dev/dtrace/riscv/dtrace_subr.c Tue Aug 2 14:50:14
2016 (r303660)
@@ -203,9 +203,9 @@ dtrace_trap(struct trapframe *frame, u_i
* All the rest will be handled in the usual way.
*/
switch (type) {
- case EXCP_LOAD_ACCESS_FAULT:
- case EXCP_STORE_ACCESS_FAULT:
- case EXCP_INSTR_ACCESS_FAULT:
+ case EXCP_FAULT_LOAD:
+ case EXCP_FAULT_STORE:
+ case EXCP_FAULT_FETCH:
/* Flag a bad address. */
cpu_core[curcpu].cpuc_dtrace_flags |=
CPU_DTRACE_BADADDR;
cpu_core[curcpu].cpuc_dtrace_illval = 0;
Modified: head/sys/conf/ldscript.riscv
==============================================================================
--- head/sys/conf/ldscript.riscv Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/conf/ldscript.riscv Tue Aug 2 14:50:14 2016
(r303660)
@@ -6,7 +6,7 @@ SEARCH_DIR(/usr/lib);
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = kernbase + 0x100;
+ . = kernbase + 0x80000000 /* KERNENTRY */;
.text : AT(ADDR(.text) - kernbase)
{
*(.text)
Modified: head/sys/riscv/conf/GENERIC
==============================================================================
--- head/sys/riscv/conf/GENERIC Tue Aug 2 14:14:36 2016 (r303659)
+++ head/sys/riscv/conf/GENERIC Tue Aug 2 14:50:14 2016 (r303660)
@@ -26,6 +26,7 @@ makeoptions DEBUG=-g # Build kernel wit
# FIXME: linker error. "--relax and -r may not be used together"
makeoptions WITHOUT_MODULES="usb otusfw mwlfw ispfw mwlfw ralfw rtwnfw
urtwnfw"
+# makeoptions NO_MODULES
options SCHED_ULE # ULE scheduler
options PREEMPTION # Enable kernel thread preemption
@@ -40,7 +41,6 @@ options UFS_ACL # Support for access
options UFS_DIRHASH # Improve performance on big directories
options UFS_GJOURNAL # Enable gjournal-based UFS journaling
options QUOTA # Enable disk quotas for UFS
-options MD_ROOT # MD is a potential root device
options NFSCL # Network Filesystem Client
options NFSD # Network Filesystem Server
options NFSLOCKD # Network Lock Manager
@@ -93,6 +93,7 @@ options INVARIANT_SUPPORT # Extra sanit
# options WITNESS_SKIPSPIN # Don't run witness on spinlocks for
speed
options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones
# options EARLY_PRINTF
+# options VERBOSE_SYSINIT
# Pseudo devices.
device loop # Network loopback
Modified: head/sys/riscv/htif/htif.c
==============================================================================
--- head/sys/riscv/htif/htif.c Tue Aug 2 14:14:36 2016 (r303659)
+++ head/sys/riscv/htif/htif.c Tue Aug 2 14:50:14 2016 (r303660)
@@ -177,11 +177,6 @@ htif_enumerate(struct htif_softc *sc)
htif_command(cmd);
- /* Do poll as interrupts are disabled yet */
- while (sc->identify_done == 0) {
- htif_handle_entry(sc);
- }
-
len = strnlen(id, sizeof(id));
if (len <= 0)
break;
Modified: head/sys/riscv/htif/htif_block.c
==============================================================================
--- head/sys/riscv/htif/htif_block.c Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/riscv/htif/htif_block.c Tue Aug 2 14:50:14 2016
(r303660)
@@ -202,6 +202,7 @@ htif_blk_task(void *arg)
uint64_t req_paddr;
struct bio *bp;
uint64_t paddr;
+ uint64_t resp;
uint64_t cmd;
int i;
@@ -239,7 +240,8 @@ htif_blk_task(void *arg)
cmd |= req_paddr;
sc->cmd_done = 0;
- htif_command(cmd);
+ resp = htif_command(cmd);
+ htif_blk_intr(sc, resp);
/* Wait for interrupt */
i = 0;
Modified: head/sys/riscv/htif/htif_console.c
==============================================================================
--- head/sys/riscv/htif/htif_console.c Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/riscv/htif/htif_console.c Tue Aug 2 14:50:14 2016
(r303660)
@@ -57,8 +57,6 @@ __FBSDID("$FreeBSD$");
#include <ddb/ddb.h>
-extern uint64_t console_intr;
-
static tsw_outwakeup_t riscvtty_outwakeup;
static struct ttydevsw riscv_ttydevsw = {
@@ -102,7 +100,7 @@ struct queue_entry *entry_last;
struct queue_entry *entry_served;
static void
-htif_putc(int c)
+riscv_putc(int c)
{
uint64_t cmd;
@@ -110,57 +108,7 @@ htif_putc(int c)
cmd |= (CONSOLE_DEFAULT_ID << HTIF_DEV_ID_SHIFT);
cmd |= c;
-#ifdef SPIN_IN_MACHINE_MODE
- machine_command(ECALL_HTIF_LOWPUTC, cmd);
-#else
- htif_command(cmd);
-#endif
-
-}
-
-static uint8_t
-htif_getc(void)
-{
- uint64_t cmd;
- uint8_t res;
-
- cmd = (HTIF_CMD_READ << HTIF_CMD_SHIFT);
- cmd |= (CONSOLE_DEFAULT_ID << HTIF_DEV_ID_SHIFT);
-
- res = htif_command(cmd);
-
- return (res);
-}
-
-static void
-riscv_putc(int c)
-{
- uint64_t counter;
- uint64_t *cc;
- uint64_t val;
-
- val = 0;
- counter = 0;
-
- cc = (uint64_t*)&console_intr;
- *cc = 0;
-
- htif_putc(c);
-
-#ifndef SPIN_IN_MACHINE_MODE
- /* Wait for an interrupt */
- __asm __volatile(
- "li %0, 1\n" /* counter = 1 */
- "slli %0, %0, 12\n" /* counter <<= 12 */
- "1:"
- "addi %0, %0, -1\n" /* counter -= 1 */
- "beqz %0, 2f\n" /* counter == 0 ? finish */
- "ld %1, 0(%2)\n" /* val = *cc */
- "beqz %1, 1b\n" /* val == 0 ? repeat */
- "2:"
- : "=&r"(counter), "=&r"(val) : "r"(cc)
- );
-#endif
+ machine_command(ECALL_HTIF_CMD, cmd);
}
#ifdef EARLY_PRINTF
@@ -272,14 +220,19 @@ riscv_cngetc(struct consdev *cp)
uint64_t entry;
uint64_t devid;
#endif
+ uint64_t cmd;
uint8_t data;
int ch;
- htif_getc();
+ cmd = (HTIF_CMD_READ << HTIF_CMD_SHIFT);
+ cmd |= (CONSOLE_DEFAULT_ID << HTIF_DEV_ID_SHIFT);
+
+ machine_command(ECALL_HTIF_CMD_REQ, cmd);
#if defined(KDB)
if (kdb_active) {
- entry = machine_command(ECALL_HTIF_GET_ENTRY, 0);
+
+ entry = machine_command(ECALL_HTIF_CMD_RESP, 0);
while (entry) {
devid = HTIF_DEV_ID(entry);
devcmd = HTIF_DEV_CMD(entry);
@@ -294,7 +247,7 @@ riscv_cngetc(struct consdev *cp)
devid);
}
- entry = machine_command(ECALL_HTIF_GET_ENTRY, 0);
+ entry = machine_command(ECALL_HTIF_CMD_RESP, 0);
}
}
#endif
Modified: head/sys/riscv/include/cpu.h
==============================================================================
--- head/sys/riscv/include/cpu.h Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/riscv/include/cpu.h Tue Aug 2 14:50:14 2016
(r303660)
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2015 Ruslan Bukin <b...@bsdpad.com>
+ * Copyright (c) 2015-2016 Ruslan Bukin <b...@bsdpad.com>
* All rights reserved.
*
* Portions of this software were developed by SRI International and the
@@ -67,11 +67,10 @@
#define CPU_PART_SHIFT 62
#define CPU_PART_MASK (0x3ul << CPU_PART_SHIFT)
-#define CPU_PART(mcpuid) ((mcpuid & CPU_PART_MASK) >>
CPU_PART_SHIFT)
-#define CPU_PART_RV32I 0x0
-#define CPU_PART_RV32E 0x1
-#define CPU_PART_RV64I 0x2
-#define CPU_PART_RV128I 0x3
+#define CPU_PART(misa) ((misa & CPU_PART_MASK) >>
CPU_PART_SHIFT)
+#define CPU_PART_RV32 0x1
+#define CPU_PART_RV64 0x2
+#define CPU_PART_RV128 0x3
extern char btext[];
extern char etext[];
Modified: head/sys/riscv/include/cpufunc.h
==============================================================================
--- head/sys/riscv/include/cpufunc.h Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/riscv/include/cpufunc.h Tue Aug 2 14:50:14 2016
(r303660)
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2015 Ruslan Bukin <b...@bsdpad.com>
+ * Copyright (c) 2015-2016 Ruslan Bukin <b...@bsdpad.com>
* All rights reserved.
*
* Portions of this software were developed by SRI International and the
@@ -54,11 +54,11 @@ intr_disable(void)
uint64_t ret;
__asm __volatile(
- "csrrci %0, sstatus, 1"
- : "=&r" (ret)
+ "csrrci %0, sstatus, %1"
+ : "=&r" (ret) : "i" (SSTATUS_SIE)
);
- return (ret & SSTATUS_IE);
+ return (ret & (SSTATUS_SIE));
}
static __inline void
@@ -76,7 +76,8 @@ intr_enable(void)
{
__asm __volatile(
- "csrsi sstatus, 1"
+ "csrsi sstatus, %0"
+ :: "i" (SSTATUS_SIE)
);
}
Modified: head/sys/riscv/include/db_machdep.h
==============================================================================
--- head/sys/riscv/include/db_machdep.h Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/riscv/include/db_machdep.h Tue Aug 2 14:50:14 2016
(r303660)
@@ -41,7 +41,7 @@
#include <machine/frame.h>
#include <machine/trap.h>
-#define T_BREAKPOINT (EXCP_INSTR_BREAKPOINT)
+#define T_BREAKPOINT (EXCP_BREAKPOINT)
#define T_WATCHPOINT (0)
typedef vm_offset_t db_addr_t;
Modified: head/sys/riscv/include/intr.h
==============================================================================
--- head/sys/riscv/include/intr.h Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/riscv/include/intr.h Tue Aug 2 14:50:14 2016
(r303660)
@@ -57,11 +57,23 @@ void riscv_unmask_ipi(void);
#endif
enum {
- IRQ_SOFTWARE,
- IRQ_TIMER,
- IRQ_HTIF,
+ IRQ_SOFTWARE_USER,
+ IRQ_SOFTWARE_SUPERVISOR,
+ IRQ_SOFTWARE_HYPERVISOR,
+ IRQ_SOFTWARE_MACHINE,
+ IRQ_TIMER_USER,
+ IRQ_TIMER_SUPERVISOR,
+ IRQ_TIMER_HYPERVISOR,
+ IRQ_TIMER_MACHINE,
+ IRQ_EXTERNAL_USER,
+ IRQ_EXTERNAL_SUPERVISOR,
+ IRQ_EXTERNAL_HYPERVISOR,
+ IRQ_EXTERNAL_MACHINE,
+#if 0
+ /* lowRISC TODO */
IRQ_COP, /* lowRISC only */
IRQ_UART, /* lowRISC only */
+#endif
NIRQS
};
Modified: head/sys/riscv/include/pte.h
==============================================================================
--- head/sys/riscv/include/pte.h Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/riscv/include/pte.h Tue Aug 2 14:50:14 2016
(r303660)
@@ -1,6 +1,6 @@
/*-
* Copyright (c) 2014 Andrew Turner
- * Copyright (c) 2015 Ruslan Bukin <b...@bsdpad.com>
+ * Copyright (c) 2015-2016 Ruslan Bukin <b...@bsdpad.com>
* All rights reserved.
*
* Portions of this software were developed by SRI International and the
@@ -66,29 +66,18 @@ typedef uint64_t pn_t; /* page
number
#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
/* Bits 9:7 are reserved for software */
-#define PTE_SW_MANAGED (1 << 8)
-#define PTE_SW_WIRED (1 << 7)
-#define PTE_DIRTY (1 << 6) /* Virtual page is written */
-#define PTE_REF (1 << 5) /* Virtual page is referenced */
-#define PTE_VALID (1 << 0) /* Virtual page is valid */
-#define PTE_TYPE_S 1
-#define PTE_TYPE_M (0xf << PTE_TYPE_S)
-#define PTE_TYPE_PTR 0
-#define PTE_TYPE_PTR_G 1
-#define PTE_TYPE_SROURX 2 /* Supervisor read-only, user
read-execute page. */
-#define PTE_TYPE_SRWURWX 3 /* Supervisor read-write, user
read-write-execute page. */
-#define PTE_TYPE_SURO 4 /* Supervisor and user read-only page.
*/
-#define PTE_TYPE_SURW 5 /* Supervisor and user read-write page.
*/
-#define PTE_TYPE_SURX 6 /* Supervisor and user read-execute
page. */
-#define PTE_TYPE_SURWX 7 /* Supervisor and User Read Write
Execute */
-#define PTE_TYPE_SRO 8 /* Supervisor read-only page. */
-#define PTE_TYPE_SRW 9 /* Supervisor read-write page. */
-#define PTE_TYPE_SRX 10 /* Supervisor read-execute page. */
-#define PTE_TYPE_SRWX 11 /* Supervisor read-write-execute page.
*/
-#define PTE_TYPE_SRO_G 12 /* Supervisor read-only page--global
mapping. */
-#define PTE_TYPE_SRW_G 13 /* Supervisor read-write page--global
mapping. */
-#define PTE_TYPE_SRX_G 14 /* Supervisor read-execute page--global
mapping. */
-#define PTE_TYPE_SRWX_G 15 /* Supervisor Read Write Execute Global
*/
+#define PTE_SW_MANAGED (1 << 9)
+#define PTE_SW_WIRED (1 << 8)
+#define PTE_D (1 << 7) /* Dirty */
+#define PTE_A (1 << 6) /* Accessed */
+#define PTE_G (1 << 5) /* Global */
+#define PTE_U (1 << 4) /* User */
+#define PTE_X (1 << 3) /* Execute */
+#define PTE_W (1 << 2) /* Write */
+#define PTE_R (1 << 1) /* Read */
+#define PTE_V (1 << 0) /* Valid */
+#define PTE_RWX (PTE_R | PTE_W | PTE_X)
+#define PTE_RX (PTE_R | PTE_X)
#define PTE_PPN0_S 10
#define PTE_PPN1_S 19
Modified: head/sys/riscv/include/riscvreg.h
==============================================================================
--- head/sys/riscv/include/riscvreg.h Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/riscv/include/riscvreg.h Tue Aug 2 14:50:14 2016
(r303660)
@@ -39,88 +39,127 @@
/* Machine mode requests */
#define ECALL_MTIMECMP 0x01
-#define ECALL_CLEAR_PENDING 0x02
-#define ECALL_HTIF_CMD 0x03
-#define ECALL_HTIF_GET_ENTRY 0x04
-#define ECALL_MCPUID_GET 0x05
-#define ECALL_MIMPID_GET 0x06
-#define ECALL_SEND_IPI 0x07
-#define ECALL_CLEAR_IPI 0x08
-#define ECALL_HTIF_LOWPUTC 0x09
-#define ECALL_MIE_SET 0x0a
-#define ECALL_IO_IRQ_MASK 0x0b
+#define ECALL_HTIF_GET_ENTRY 0x02
+#define ECALL_MCPUID_GET 0x03
+#define ECALL_MIMPID_GET 0x04
+#define ECALL_SEND_IPI 0x05
+#define ECALL_CLEAR_IPI 0x06
+#define ECALL_MIE_SET 0x07
+#define ECALL_IO_IRQ_MASK 0x08
+#define ECALL_HTIF_CMD 0x09
+#define ECALL_HTIF_CMD_REQ 0x0a
+#define ECALL_HTIF_CMD_RESP 0x0b
#define EXCP_SHIFT 0
#define EXCP_MASK (0xf << EXCP_SHIFT)
-#define EXCP_INSTR_ADDR_MISALIGNED 0
-#define EXCP_INSTR_ACCESS_FAULT 1
-#define EXCP_INSTR_ILLEGAL 2
-#define EXCP_INSTR_BREAKPOINT 3
-#define EXCP_LOAD_ADDR_MISALIGNED 4
-#define EXCP_LOAD_ACCESS_FAULT 5
-#define EXCP_STORE_ADDR_MISALIGNED 6
-#define EXCP_STORE_ACCESS_FAULT 7
-#define EXCP_UMODE_ENV_CALL 8
-#define EXCP_SMODE_ENV_CALL 9
-#define EXCP_HMODE_ENV_CALL 10
-#define EXCP_MMODE_ENV_CALL 11
-#define EXCP_INTR (1 << 31)
+#define EXCP_MISALIGNED_FETCH 0
+#define EXCP_FAULT_FETCH 1
+#define EXCP_ILLEGAL_INSTRUCTION 2
+#define EXCP_BREAKPOINT 3
+#define EXCP_MISALIGNED_LOAD 4
+#define EXCP_FAULT_LOAD 5
+#define EXCP_MISALIGNED_STORE 6
+#define EXCP_FAULT_STORE 7
+#define EXCP_USER_ECALL 8
+#define EXCP_SUPERVISOR_ECALL 9
+#define EXCP_HYPERVISOR_ECALL 10
+#define EXCP_MACHINE_ECALL 11
+#define EXCP_INTR (1ul << 63)
#define EXCP_INTR_SOFTWARE 0
#define EXCP_INTR_TIMER 1
#define EXCP_INTR_HTIF 2
-#define SSTATUS_IE (1 << 0)
-#define SSTATUS_PIE (1 << 3)
-#define SSTATUS_PS (1 << 4)
-
-#define MSTATUS_MPRV (1 << 16)
-#define MSTATUS_PRV_SHIFT 1
-#define MSTATUS_PRV1_SHIFT 4
-#define MSTATUS_PRV2_SHIFT 7
-#define MSTATUS_PRV_MASK (0x3 << MSTATUS_PRV_SHIFT)
-#define MSTATUS_PRV_U 0 /* user */
-#define MSTATUS_PRV_S 1 /* supervisor */
-#define MSTATUS_PRV_H 2 /* hypervisor */
-#define MSTATUS_PRV_M 3 /* machine */
-
-#define MSTATUS_VM_SHIFT 17
-#define MSTATUS_VM_MASK 0x1f
-#define MSTATUS_VM_MBARE 0
-#define MSTATUS_VM_MBB 1
-#define MSTATUS_VM_MBBID 2
-#define MSTATUS_VM_SV32 8
-#define MSTATUS_VM_SV39 9
-#define MSTATUS_VM_SV48 10
+#define SSTATUS_UIE (1 << 0)
+#define SSTATUS_SIE (1 << 1)
+#define SSTATUS_UPIE (1 << 4)
+#define SSTATUS_SPIE (1 << 5)
+#define SSTATUS_SPIE_SHIFT 5
+#define SSTATUS_SPP (1 << 8)
+#define SSTATUS_SPP_SHIFT 8
+#define SSTATUS_FS_MASK 0x3
+#define SSTATUS_FS_SHIFT 13
+#define SSTATUS_XS_MASK 0x3
+#define SSTATUS_XS_SHIFT 15
+#define SSTATUS_PUM (1 << 18)
+#define SSTATUS32_SD (1 << 63)
+#define SSTATUS64_SD (1 << 31)
+
+#define MSTATUS_UIE (1 << 0)
+#define MSTATUS_SIE (1 << 1)
+#define MSTATUS_HIE (1 << 2)
+#define MSTATUS_MIE (1 << 3)
+#define MSTATUS_UPIE (1 << 4)
+#define MSTATUS_SPIE (1 << 5)
+#define MSTATUS_SPIE_SHIFT 5
+#define MSTATUS_HPIE (1 << 6)
+#define MSTATUS_MPIE (1 << 7)
+#define MSTATUS_MPIE_SHIFT 7
+#define MSTATUS_SPP (1 << 8)
+#define MSTATUS_SPP_SHIFT 8
+#define MSTATUS_HPP_MASK 0x3
+#define MSTATUS_HPP_SHIFT 9
+#define MSTATUS_MPP_MASK 0x3
+#define MSTATUS_MPP_SHIFT 11
+#define MSTATUS_FS_MASK 0x3
+#define MSTATUS_FS_SHIFT 13
+#define MSTATUS_XS_MASK 0x3
+#define MSTATUS_XS_SHIFT 15
+#define MSTATUS_MPRV (1 << 17)
+#define MSTATUS_PUM (1 << 18)
+#define MSTATUS_VM_MASK 0x1f
+#define MSTATUS_VM_SHIFT 24
+#define MSTATUS_VM_MBARE 0
+#define MSTATUS_VM_MBB 1
+#define MSTATUS_VM_MBBID 2
+#define MSTATUS_VM_SV32 8
+#define MSTATUS_VM_SV39 9
+#define MSTATUS_VM_SV48 10
+#define MSTATUS_VM_SV57 11
+#define MSTATUS_VM_SV64 12
+#define MSTATUS32_SD (1 << 63)
+#define MSTATUS64_SD (1 << 31)
+
+#define MSTATUS_PRV_U 0 /* user */
+#define MSTATUS_PRV_S 1 /* supervisor */
+#define MSTATUS_PRV_H 2 /* hypervisor */
+#define MSTATUS_PRV_M 3 /* machine */
+#define MIE_USIE (1 << 0)
#define MIE_SSIE (1 << 1)
#define MIE_HSIE (1 << 2)
#define MIE_MSIE (1 << 3)
+#define MIE_UTIE (1 << 4)
#define MIE_STIE (1 << 5)
#define MIE_HTIE (1 << 6)
#define MIE_MTIE (1 << 7)
+#define MIP_USIP (1 << 0)
#define MIP_SSIP (1 << 1)
#define MIP_HSIP (1 << 2)
#define MIP_MSIP (1 << 3)
+#define MIP_UTIP (1 << 4)
#define MIP_STIP (1 << 5)
#define MIP_HTIP (1 << 6)
#define MIP_MTIP (1 << 7)
-#define SR_IE (1 << 0)
-#define SR_IE1 (1 << 3)
-#define SR_IE2 (1 << 6)
-#define SR_IE3 (1 << 9)
-
+#define SIE_USIE (1 << 0)
#define SIE_SSIE (1 << 1)
+#define SIE_UTIE (1 << 4)
#define SIE_STIE (1 << 5)
+#define MIP_SEIP (1 << 9)
+
/* Note: sip register has no SIP_STIP bit in Spike simulator */
#define SIP_SSIP (1 << 1)
#define SIP_STIP (1 << 5)
+#if 0
+/* lowRISC TODO */
#define NCSRS 4096
#define CSR_IPI 0x783
#define CSR_IO_IRQ 0x7c0 /* lowRISC only? */
+#endif
+
#define XLEN 8
#define INSN_SIZE 4
Modified: head/sys/riscv/include/vmparam.h
==============================================================================
--- head/sys/riscv/include/vmparam.h Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/riscv/include/vmparam.h Tue Aug 2 14:50:14 2016
(r303660)
@@ -196,7 +196,7 @@
#define SHAREDPAGE (VM_MAXUSER_ADDRESS - PAGE_SIZE)
#define USRSTACK SHAREDPAGE
-#define KERNENTRY (0x200)
+#define KERNENTRY (0x80000000)
/*
* How many physical pages per kmem arena virtual page.
Modified: head/sys/riscv/riscv/exception.S
==============================================================================
--- head/sys/riscv/riscv/exception.S Tue Aug 2 14:14:36 2016
(r303659)
+++ head/sys/riscv/riscv/exception.S Tue Aug 2 14:50:14 2016
(r303660)
@@ -117,14 +117,15 @@ __FBSDID("$FreeBSD$");
ld t0, (TF_SSTATUS)(sp)
.if \el == 0
/* Ensure user interrupts will be enabled on eret. */
- ori t0, t0, SSTATUS_PIE
+ li t1, SSTATUS_SPIE
+ or t0, t0, t1
.else
/*
* Disable interrupts for supervisor mode exceptions.
* For user mode exceptions we have already done this
* in do_ast.
*/
- li t1, ~SSTATUS_IE
+ li t1, ~SSTATUS_SIE
and t0, t0, t1
.endif
csrw sstatus, t0
@@ -182,7 +183,7 @@ __FBSDID("$FreeBSD$");
/* Disable interrupts */
csrr a4, sstatus
1:
- csrci sstatus, SSTATUS_IE
+ csrci sstatus, (SSTATUS_SIE)
ld a1, PC_CURTHREAD(gp)
lw a2, TD_FLAGS(a1)
@@ -192,7 +193,7 @@ __FBSDID("$FreeBSD$");
beqz a2, 2f
/* Restore interrupts */
- andi a4, a4, SSTATUS_IE
+ andi a4, a4, (SSTATUS_SIE)
csrs sstatus, a4
/* Handle the ast */
@@ -204,12 +205,24 @@ __FBSDID("$FreeBSD$");
2:
.endm
+ENTRY(cpu_exception_handler)
+ csrrw sp, sscratch, sp
+ beqz sp, 1f
+ /* User mode detected */
+ csrrw sp, sscratch, sp
+ j cpu_exception_handler_user
+1:
+ /* Supervisor mode detected */
+ csrrw sp, sscratch, sp
+ j cpu_exception_handler_supervisor
+END(cpu_exception_handler)
+
ENTRY(cpu_exception_handler_supervisor)
save_registers 1
mv a0, sp
call _C_LABEL(do_trap_supervisor)
load_registers 1
- eret
+ sret
END(cpu_exception_handler_supervisor)
ENTRY(cpu_exception_handler_user)
@@ -220,7 +233,7 @@ ENTRY(cpu_exception_handler_user)
do_ast
load_registers 0
csrrw sp, sscratch, sp
- eret
+ sret
END(cpu_exception_handler_user)
/*
@@ -230,7 +243,7 @@ END(cpu_exception_handler_user)
bad_trap:
j bad_trap
-user_trap:
+machine_trap:
/* Save state */
csrrw sp, mscratch, sp
addi sp, sp, -64
@@ -242,91 +255,84 @@ user_trap:
sd t5, (8 * 5)(sp)
sd a0, (8 * 7)(sp)
- la t2, _C_LABEL(cpu_exception_handler_user)
-
- csrr t0, mcause
- bltz t0, machine_interrupt
- j exit_mrts
-
-supervisor_trap:
- /* Save state */
- csrrw sp, mscratch, sp
- addi sp, sp, -64
- sd t0, (8 * 0)(sp)
- sd t1, (8 * 1)(sp)
- sd t2, (8 * 2)(sp)
- sd t3, (8 * 3)(sp)
- sd t4, (8 * 4)(sp)
- sd t5, (8 * 5)(sp)
- sd a0, (8 * 7)(sp)
-
- la t2, _C_LABEL(cpu_exception_handler_supervisor)
-
+ csrr t3, mstatus /* Required for debug */
csrr t0, mcause
bltz t0, machine_interrupt
- li t1, EXCP_SMODE_ENV_CALL
+ li t1, EXCP_SUPERVISOR_ECALL
beq t0, t1, supervisor_call
- j exit_mrts
+4:
+ /* NOT REACHED */
+ j 4b
machine_interrupt:
/* Type of interrupt ? */
csrr t0, mcause
andi t0, t0, EXCP_MASK
- li t1, 0
- beq t1, t0, software_interrupt
- li t1, 1
- beq t1, t0, timer_interrupt
- li t1, 2
- beq t1, t0, htif_interrupt
+#if 0
+ /* lowRISC TODO */
li t1, 4
beq t1, t0, io_interrupt /* lowRISC only */
+#endif
+ li t1, 1
+ beq t1, t0, supervisor_software_interrupt
+ li t1, 3
+ beq t1, t0, machine_software_interrupt
+ li t1, 5
+ beq t1, t0, supervisor_timer_interrupt
+ li t1, 7
+ beq t1, t0, machine_timer_interrupt
- /* not reached */
+ /* NOT REACHED */
1:
j 1b
+#if 0
+ /* lowRISC TODO */
io_interrupt:
/* Disable IO interrupts so we can go to supervisor mode */
csrwi CSR_IO_IRQ, 0
/* Handle the trap in supervisor mode */
j exit_mrts
+#endif
+
+supervisor_software_interrupt:
+1:
+ /* Nothing here as we are using mideleg feature */
+ j 1b
+
+machine_software_interrupt:
+ /* Clear IPI */
+ li t0, 0x40001000
+ csrr t2, mhartid
+ li t3, 0x1000
+ mul t2, t2, t3
+ add t0, t0, t2
+ li t2, 0
+ sd t2, 0(t0)
-software_interrupt:
+ /* Clear machine software pending bit */
li t0, MIP_MSIP
csrc mip, t0
+
+ /* Post supervisor software interrupt */
li t0, MIP_SSIP
csrs mip, t0
- /* If PRV1 is PRV_U (user) then serve the trap */
- csrr t0, mstatus
- li t1, (MSTATUS_PRV_M << MSTATUS_PRV1_SHIFT)
- and t0, t0, t1
- beqz t0, 1f
-
- /*
- * If PRV1 is supervisor and interrupts were enabled,
- * then serve the trap.
- */
- csrr t0, mstatus
- li t1, (SR_IE1 | (MSTATUS_PRV_M << MSTATUS_PRV1_SHIFT))
- and t0, t0, t1
- li t1, (SR_IE1 | (MSTATUS_PRV_S << MSTATUS_PRV1_SHIFT))
- beq t0, t1, 1f
-
j exit
+supervisor_timer_interrupt:
1:
- /* Handle the trap in supervisor mode */
- j exit_mrts
+ /* Nothing here as we are using mideleg feature */
+ j 1b
-timer_interrupt:
+machine_timer_interrupt:
/* Disable machine timer interrupts */
li t0, MIE_MTIE
csrc mie, t0
- /* Clear machine pending */
+ /* Clear machine timer interrupt pending */
li t0, MIP_MTIP
csrc mip, t0
@@ -334,54 +340,32 @@ timer_interrupt:
li t0, MIP_STIP
csrs mip, t0
- /* If PRV1 is PRV_U (user) then serve the trap */
- csrr t0, mstatus
- li t1, (MSTATUS_PRV_M << MSTATUS_PRV1_SHIFT)
- and t0, t0, t1
- beqz t0, 1f
-
/*
- * If PRV1 is supervisor and interrupts were enabled,
- * then serve the trap.
+ * Check for HTIF interrupts.
+ * The only interrupt expected here is key press.
*/
- csrr t0, mstatus
- li t1, (SR_IE1 | (MSTATUS_PRV_M << MSTATUS_PRV1_SHIFT))
- and t0, t0, t1
- li t1, (SR_IE1 | (MSTATUS_PRV_S << MSTATUS_PRV1_SHIFT))
- beq t0, t1, 1f
-
- j exit
-
-1:
- /* Serve a trap in supervisor mode */
- j exit_mrts
+ la t0, htif_lock
+ li t2, 1
+ amoswap.d t3, t2, 0(t0)
+ bnez t3, 5f /* Another operation in progress, give up */
-htif_interrupt:
-1:
- li t5, 0
- csrrw t5, mfromhost, t5
- beqz t5, 3f
+ /* We have lock */
+ la t1, fromhost
+ ld t5, 0(t1)
+ beqz t5, 4f
- /* Console PUT intr ? */
+ /* Console GET intr ? */
mv t1, t5
- li t0, 0x101
+ li t0, 0x100
srli t1, t1, 48
- bne t1, t0, 2f
- /* Yes */
- la t0, console_intr
- li t1, 1
- sd t1, 0(t0)
-
- /* Check if there is any other pending event */
+ beq t1, t0, 2f
+1:
+ /* There is no interrupts except keypress */
j 1b
2:
/* Save entry */
la t0, htif_ring
- csrr t1, mhartid
- li t4, (HTIF_RING_SIZE + 16)
- mulw t4, t4, t1
- add t0, t0, t4
li t4, (HTIF_RING_SIZE)
add t0, t0, t4 /* t0 == htif_ring_cursor */
@@ -397,10 +381,18 @@ htif_interrupt:
li t0, MIP_SSIP
csrs mip, t0
- /* Check if there is any other pending event */
- j 1b
-
3:
+ la t1, fromhost
+ li t5, 0
+ sd t5, 0(t1)
+
+4:
+ /* Release lock */
+ la t0, htif_lock
+ li t2, 0
+ amoswap.d t3, t2, 0(t0)
+
+5:
j exit
supervisor_call:
@@ -408,12 +400,14 @@ supervisor_call:
addi t1, t1, 4 /* Next instruction in t1 */
li t4, ECALL_HTIF_CMD
beq t5, t4, htif_cmd
+ li t4, ECALL_HTIF_CMD_REQ
+ beq t5, t4, htif_cmd_req
+ li t4, ECALL_HTIF_CMD_RESP
+ beq t5, t4, htif_cmd_resp
li t4, ECALL_HTIF_GET_ENTRY
beq t5, t4, htif_get_entry
li t4, ECALL_MTIMECMP
beq t5, t4, set_mtimecmp
- li t4, ECALL_CLEAR_PENDING
- beq t5, t4, clear_pending
li t4, ECALL_MCPUID_GET
beq t5, t4, mcpuid_get
li t4, ECALL_MIMPID_GET
@@ -422,24 +416,28 @@ supervisor_call:
beq t5, t4, send_ipi
li t4, ECALL_CLEAR_IPI
beq t5, t4, clear_ipi
- li t4, ECALL_HTIF_LOWPUTC
- beq t5, t4, htif_lowputc
li t4, ECALL_MIE_SET
beq t5, t4, mie_set
+#if 0
+ /* lowRISC TODO */
li t4, ECALL_IO_IRQ_MASK
beq t5, t4, io_irq_mask
+#endif
j exit_next_instr
+#if 0
+ /* lowRISC TODO */
io_irq_mask:
csrw CSR_IO_IRQ, t6
j exit_next_instr
+#endif
mie_set:
csrs mie, t6
j exit_next_instr
mcpuid_get:
- csrr t6, mcpuid
+ csrr t6, misa
j exit_next_instr
mimpid_get:
@@ -447,10 +445,8 @@ mimpid_get:
j exit_next_instr
send_ipi:
- /* CPU mmio base in t6 */
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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