Current ioctl(CMD_MSG_RECV) contains an expensive cache operation. Even if
the data is quite small, it always executes D-Cache flush on a buffer
at minimum unit of one page in kdbus_conn_msg_install() /
kdbus_pool_slice_flush() .
In fact, flush_dcache_page() implementation is very expensive on ARM
On 06/25/2014 11:13 AM, AKASHI Takahiro wrote:
> Current ioctl(CMD_MSG_RECV) contains an expensive cache operation. Even if
> the data is quite small, it always executes D-Cache flush on a buffer
> at minimum unit of one page in kdbus_conn_msg_install() /
> kdbus_pool_slice_flush() .
> In fact, flu
n 06/25/2014 07:03 PM, Daniel Mack wrote:
On 06/25/2014 11:13 AM, AKASHI Takahiro wrote:
Current ioctl(CMD_MSG_RECV) contains an expensive cache operation. Even if
the data is quite small, it always executes D-Cache flush on a buffer
at minimum unit of one page in kdbus_conn_msg_install() /
kdbu
Hi,
I now booted an ARM board and tried your change, but it doesn't work.
On 06/25/2014 11:13 AM, AKASHI Takahiro wrote:
> void kdbus_pool_slice_flush(const struct kdbus_pool_slice *slice)
> {
> +#if KDBUS_HACK3
> + flush_kernel_vmap_range((void *)slice->off, slice->size);
slice->off is th
On 06/27/2014 01:17 AM, Daniel Mack wrote:
Hi,
I now booted an ARM board and tried your change, but it doesn't work.
On 06/25/2014 11:13 AM, AKASHI Takahiro wrote:
void kdbus_pool_slice_flush(const struct kdbus_pool_slice *slice)
{
+#if KDBUS_HACK3
+ flush_kernel_vmap_range((void *)s
On 06/27/2014 10:50 AM, AKASHI Takahiro wrote:
> On 06/27/2014 01:17 AM, Daniel Mack wrote:
>> Your Pandaboard features an OMAP4430 MCU with VIPT/PIPT data cache that
>> doesn't suffer from aliasing, and both cache_is_vivt() and
>> cache_is_vipt_aliasing() will validate to false on your platform.
