Re: amd64: simplify TSC sync testing

2022-02-02 Thread Mohamed Aslan
Hello, I can confirm the same behaviour with this patch applied. $ sysctl kern.timecounter kern.timecounter.tick=1 kern.timecounter.timestepwarnings=0 kern.timecounter.hardware=i8254 kern.timecounter.choice=i8254(0) tsc(-1000) acpihpet0(1000) acpitimer0(1000) $ sysctl hw hw.machine=amd64 hw.mode

vmd: enable pause/unpause for vm owners

2018-04-15 Thread Mohamed Aslan
Hello tech@, I noticed that vmd(8) only allows VM owners to start/stop their VMs, but does not let them to pause/unpause those VMs. I was just wondering if there are reasons behind that. If not, the patch below enables pause/unpause commands for VM owners. Regards, Aslan Index: control.c ===

Re: Microkernel

2022-05-21 Thread Mohamed Aslan
A decade ago, there was an experiment to port OpenBSD to the L4/Fiasco microkernel [1]. However, if I remember correctly, it was not a multi-server port, someone please correct me if i am wrong. Regards, Aslan [1] https://www.isti.tu-berlin.de/fileadmin/fg214/finished_theses/cludwig/OpenBSDonFi

Re: [v3] amd64: simplify TSC sync testing

2022-07-05 Thread Mohamed Aslan
t; /* > - * Synchronize the TSC for the first time. Note that interrupts are > - * off at this point. > + * Test if our TSC is synchronized for the first time. > + * Note that interrupts are off at this point. >*/ > wbinvd(); > ci->ci_flags |= CPUF_PRESENT; > - ci->ci_tsc_skew = 0;/* reset on resume */ > - tsc_sync_ap(ci); > + tsc_test_sync_ap(ci); > > lapic_enable(); > lapic_startclock(); > Index: include/cpu.h > === > RCS file: /cvs/src/sys/arch/amd64/include/cpu.h,v > retrieving revision 1.144 > diff -u -p -r1.144 cpu.h > --- include/cpu.h 28 Jun 2022 12:11:41 - 1.144 > +++ include/cpu.h 5 Jul 2022 01:52:11 - > @@ -209,8 +209,6 @@ struct cpu_info { > paddr_t ci_vmxon_region_pa; > struct vmxon_region *ci_vmxon_region; > > - int64_t ci_tsc_skew;/* counter skew vs cpu0 */ > - > charci_panicbuf[512]; > > paddr_t ci_vmcs_pa; > @@ -230,7 +228,6 @@ struct cpu_info { > #define CPUF_INVAR_TSC 0x0100 /* CPU has invariant TSC */ > #define CPUF_USERXSTATE 0x0200 /* CPU has curproc's xsave > state */ > > -#define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ > #define CPUF_PRESENT 0x1000 /* CPU is present */ > #define CPUF_RUNNING 0x2000 /* CPU is running */ > #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ > Index: include/cpuvar.h > === > RCS file: /cvs/src/sys/arch/amd64/include/cpuvar.h,v > retrieving revision 1.11 > diff -u -p -r1.11 cpuvar.h > --- include/cpuvar.h 16 May 2021 04:33:05 - 1.11 > +++ include/cpuvar.h 5 Jul 2022 01:52:11 - > @@ -97,8 +97,7 @@ void identifycpu(struct cpu_info *); > void cpu_init(struct cpu_info *); > void cpu_init_first(void); > > -void tsc_sync_drift(int64_t); > -void tsc_sync_bp(struct cpu_info *); > -void tsc_sync_ap(struct cpu_info *); > +void tsc_test_sync_bp(struct cpu_info *); > +void tsc_test_sync_ap(struct cpu_info *); > > #endif > -- Mohamed 'Aslan' Abdelsalam, Ph.D. http://www.sce.carleton.ca/~maslan/

Re: [v3] amd64: simplify TSC sync testing

2022-07-05 Thread Mohamed Aslan
What I meant in my first email is, it seems that before applying your patch, the tsc was used as the hardware counter (no user TSC though), but after applying your patch the i8254 was the one being used. Thanks On Tue, Jul 05, 2022 at 10:34:54PM -0400, Mohamed Aslan wrote: > Sorry the `sys

Re: [v3] amd64: simplify TSC sync testing

2022-07-05 Thread Mohamed Aslan
n Tue, Jul 05, 2022 at 10:31:33PM -0400, Mohamed Aslan wrote: > Hello, > > I just tested your patch on my lenovo e495 laptop, unfortunately > still no tsc. > > $ dmesg | grep 'tsc:' > tsc: cpu0/cpu1 sync round 1: 20468 regressions > tsc: cpu0/cpu1 sync round 1: cp

Re: [SPAM] Re: [v3] amd64: simplify TSC sync testing

2022-07-05 Thread Mohamed Aslan
2 configuration 1 interface 0 "Chicony Electronics Co.,Ltd. Integrated Camera" rev 2.01/26.99 addr 3 video0 at uvideo0 vscsi0 at root scsibus2 at vscsi0: 256 targets softraid0 at root scsibus3 at softraid0: 256 targets sd1 at scsibus3 targ 1 lun 0: sd1: 223231MB, 512 bytes/sector,

Re: [v3] amd64: simplify TSC sync testing

2022-07-05 Thread Mohamed Aslan
> This is expected behavior with the patch. > > cpu0's TSC is way out of sync with every > other CPU's TSC, so the TSC is marked > as a bad timecounter and a different one is > chosen. Yes, I can see. Just want to add that without your latest patch the kernel chooses the TSC as clocksource, howev

Re: [v3] amd64: simplify TSC sync testing

2022-07-06 Thread Mohamed Aslan
> First, you need to update to the latest firmware. Maybe they already > fixed the problem. I don't see any mention of the TSC in the BIOS > changelog for the e495 but maybe you'll get lucky. > > Second, if they haven't fixed the problem with the latest firmware, I > recommend you reach out to L

Re: Secure by default

2021-02-13 Thread Mohamed Aslan
How's is this related to tech@? On Sun, Feb 14, 2021 at 12:44:00AM +0530, sivasubramanian muthusamy wrote: > Hello, > > I am an ordinary computer user, installed 6.8 without connecting to > the Internet yet, (a friend and a technical expert recently advised me > in a different context: do not exp