On Sun, Mar 18, 2018 at 06:33:59PM +0100, Mark Kettenis wrote:
> > Date: Sun, 18 Mar 2018 12:17:09 +
> > From: Visa Hankala
> >
> > On Sat, Mar 17, 2018 at 07:41:39PM +0100, Mark Kettenis wrote:
> > > Index: dev/sdmmc/sdhc.c
> > > ==
> Date: Sun, 18 Mar 2018 12:17:09 +
> From: Visa Hankala
>
> On Sat, Mar 17, 2018 at 07:41:39PM +0100, Mark Kettenis wrote:
> > Index: dev/sdmmc/sdhc.c
> > ===
> > RCS file: /cvs/src/sys/dev/sdmmc/sdhc.c,v
> > retrieving revision
On Sat, Mar 17, 2018 at 07:41:39PM +0100, Mark Kettenis wrote:
> Index: dev/sdmmc/sdhc.c
> ===
> RCS file: /cvs/src/sys/dev/sdmmc/sdhc.c,v
> retrieving revision 1.56
> diff -u -p -r1.56 sdhc.c
> --- dev/sdmmc/sdhc.c 10 Feb 2018 05:21:
The SDHC controller found on the Marvell Armada 7K and 8K SoCs has all
the base clock frequency bits in the capabilities register set to 0.
The SDHC 3.0 spec says that this means that "the Host System has to
get the information via another method". This diff provides that
method. The sdhc(4) bus
