On Tue, Jun 23, 2020 at 11:14:30PM +0200, Jaromír Dole?ek wrote:
> No lazy FPU save logic please. It was eradicated from x86 for a reason:
> https://access.redhat.com/solutions/3485131
Taylor added code (in the proposed changes, not for general x86 context
switches) to avoid leaks like that in his
Le mar. 23 juin 2020 à 00:14, Eduardo Horvath a écrit :
> The SPARC has always had a lazy FPU save logic. The fpstate structure is
> not part of the pcb and is allocated on first use.
No lazy FPU save logic please. It was eradicated from x86 for a reason:
https://access.redhat.com/solutions/3485
On 2020/06/19 3:17, SAITOH Masanobu wrote:
Hi.
I'm now working to reduce ixgbe's busy loop using with kpause()[*1].
I wrote the following code:
#define usec_delay(x) ixgbe_delay(x)
#define msec_delay(x) ixgbe_delay((x) * 1000)
void
ixgbe_delay(unsigned int us)
{
if (__predict_false(
On Tue, Jun 23, 2020 at 01:26:21PM +0200, Reinoud Zandijk wrote:
> Is there any hope for adding this? Does the default ATI/AMD Radeon driver
> support this and is this thus just a missing detection in drmkms?
No, the radeon driver does not support this. The amdgpu driver does,
but that isn't ready
Hi folks,
my old videocard died and I replaced it with a slightly newer one but it isn't
recognized and nothing other than vga0 attaches. Its an Gigabyte Radeon RX460
with 2 GB ram.
002:00:0: ATI Technologies Radeon RX460 (VGA display, revision 0xcf)
002:00:1: ATI Technologies Radeon RX 460/550/6
a data point on a machine from 2014:
$ ./aestest -l
BearSSL aes_ct
Intel SSE2 bitsliced
$ progress -f /dev/zero sh -c 'exec ./aestest -e -b 256 -c aes-xts -i "Intel
SSE2 bitsliced" > /dev/null'
399 MiB 56.98 MiB/s ^C
$ progress -f /dev/zero sh -c 'exec ./aestest -e -b 256 -c aes-xts -i "Bea
Taylor R Campbell writes:
>> What I meant is: consider an external USB disk of say 4T, which has a
>> cgd partition within which is ffs.
>>
>> Someone attaches it to several systems in turn, doing cgd_attach, mount,
>> and then runs bup with /mnt/bup as the target, getting deduplication
>> acros
On Thu, Jun 18, 2020 at 08:21:36PM -0400, Greg Troxel wrote:
> So it remains to make userland AES use also constant time, as a separate
> step?
For userland AES, we are mostly using OpenSSL.
There was a bug recently in the in-src copy of OpenSSL that prevented it
from detecting the CPU type prope
