Hello to everyone,
I'm new to the list and would like to ask about displaying the upcoming
leap second on a linux workstation.
I use a PC running linux 2.6.24 and the djb clockspeed daemon periodically
synchronized with a couple of different NTP servers. I usually have a
correct
I'm new to the list and would like to ask about displaying the
upcoming leap second on a linux workstation.
Stick around. There will be a big party.
You might check the archives to see the discussion from the last one.
I've done quite a bit of scroogling in an attempt to determine how
2008/7/9 wje [EMAIL PROTECTED]:
www.hparchive.com/Manuals/HP-10811AB-Manual.pdf
These seem to be a slight variation on the 10811B, but I imagine the
pinouts are the same, other than the connectors.
Hmm... I think I'll get one.
Bill Ezell
--
They said 'Windows or better'
so
In my best HAL 9000 voice;
Hi Dave. Dave, what are you doing ? Dave we need BNC connectors. Those SMB's
are hard to work with. Dave, are you intending to have those SMB's stick out
through a panel ? Dave ? Dave, let me suggest that you layout the connector
pattern so either one can be used
I am not a big fan of BNC connectors on the PC board itself, because I am
not a big fan of attaching PC boards directly to panels in most cases.
There are usually some BNC bulkhead connectors on eBay that terminate in
SMA/SMB/SMC pigtails, which are great for panel mounting.
From: David C. Partridge [EMAIL PROTECTED]
Subject: [time-nuts] Frequency divider design critique request
Date: Thu, 10 Jul 2008 21:30:56 +0100
Message-ID: [EMAIL PROTECTED]
David,
As I've mentioned before, I've been working on the design of a frequency
divider to go with my TB.
The idea is
Hej Magnus
Magnus Danielson wrote:
David,
As I've mentioned before, I've been working on the design of a frequency
divider to go with my TB.
The idea is 10MHz sine in from TB, output 2.5Vp-p 50% duty cycle square wave
into 50R (5V into 1M), at 10Mhz, 5MHz, 1MHz and decade selectable
Hi David,
It looks like your design is pretty far along, so maybe it's too late for this
suggestion, but one thing you might consider is replacing the 7400 series logic
with a 5V CPLD programmable logic device.
This could offer several advantages:
1) any issues (such as jitter) could be
[EMAIL PROTECTED] wrote:
Hi David,
It looks like your design is pretty far along, so maybe it's too late for
this suggestion, but one thing you might consider is replacing the 7400
series logic with a 5V CPLD programmable logic device.
This could offer several advantages:
1) any issues
Magnus Danielson wrote:
I would consider a dedicated 1 PPS output.
I would consider a synchronise feature with a PPS/synchronise input. It should
be wise to not directly wire it to the counter resets, but provide an arm
button and maybe a very simple arrangement to indicate left, on mark and
The CPLD's (unlike the FPGAs) are single chip solutions.
There are many single chip FPGA solutions today from several different
companies.
If you are in the US and near a Avnet office you can pick up a Actel
Igloo Icicle
eval. board/programmer for $49. They are giving them out at the Actel
On Fri, Jul 11, 2008 at 11:33:53AM +1200, Bruce Griffiths wrote:
[EMAIL PROTECTED] wrote:
Hi David,
It looks like your design is pretty far along, so maybe it's too late for
this suggestion, but one thing you might consider is replacing the 7400
series logic with a 5V CPLD
The TrueTime XL-AK Time Frequency Receiver does just what you want plus
a few more outputs. Unfortunately they do not provide schematics in the
manual.
73, Dick, W1KSZ
-Original Message-
From: David C. Partridge [EMAIL PROTECTED]
Sent: Jul 10, 2008 1:30 PM
To: 'Discussion of precise
John Miles wrote:
I am not a big fan of BNC connectors on the PC board itself, because I
am not a big fan of attaching PC boards directly to panels in most cases.
There are usually some BNC bulkhead connectors on eBay that terminate
in SMA/SMB/SMC pigtails, which are great for panel
Bruce wrote.
However this adds considerable complexity and would be much easier to
implement in a CPLD or FPGA.
John and I have a design sketch based on a CoolRunner-2 CPLD that we have
been kicking around as a potential TAPR board. The CR2 is nice in that the
flip flops can be clocked on
christopher hoover wrote, in part,
John and I have both been preoccupied with Life over the last N months
and haven't gotten back to the project yet.
I can identify with that. Back in the 70's, Life was a cellular automata
display on primitive computers. I wrote a routine to plot the population
Old news but is an example of the real word consequences of bad time keeping /
bad programing.
http://www.cs.usyd.edu.au/~alum/patriot_bug.html
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