On Thu, Feb 28, 2013 at 6:08 AM, Daniel Mendes wrote:
>
> Thanks for all the comments about this topic. They are much appreciated.
>
> About the difficulty of measuring every cycle with a conventional counter...
> thanks for that info, seems that i´ll have to make my own measurement
> hardware. I
Ok, it´s a relative measurement... now I understand your data. Thank you.
Daniel
Em 28/02/2013 20:03, Tom Van Baak (lab) escreveu:
Yes, correct, sometimes the power line goes faster than 60 Hz in which case the
zero-crossings occur before you "expect them"; so time error can be negative,
on
Javier:
the 24bit counter is clocked only by the 10MHz and is running continuously,
the PPS is the most important signal. The LSClock is the clock for the
latch: this latch has to be clocked to shift out its content serially and
has to be loaded with the PPS from the GPS (PPSReference). I see no ot
Yes, correct, sometimes the power line goes faster than 60 Hz in which case the
zero-crossings occur before you "expect them"; so time error can be negative,
on average, as often as it is positive.
You cannot design a PLL that always expects phase error to be unidirectional.
The data I provided
Em 28/02/2013 13:37, Tom Van Baak escreveu:
Daniel,
I've placed two log files for you under http://leapsecond.com/pages/mains/
log1932.dat.gz -- timing of every 60 Hz zero-crossing (1.296 million samples)
log97312.dat.gz -- timing of every 60th zero-crossing (21.6 thousand samples)
Each repres
On 2/28/2013 11:37 AM, time-nuts-requ...@febo.com wrote:
About the difficulty of measuring every cycle with a conventional
counter... thanks for that info, seems that i?ll have to make my own
measurement hardware. I liked the idea of a time stamping counter
it?s very doable in a FPGA:)
At
Daniel,
I've placed two log files for you under http://leapsecond.com/pages/mains/
log1932.dat.gz -- timing of every 60 Hz zero-crossing (1.296 million samples)
log97312.dat.gz -- timing of every 60th zero-crossing (21.6 thousand samples)
Each represents 6 hours of collection time. Units are sec
On Thu, Feb 28, 2013 at 1:26 AM, Azelio Boriani
wrote:
> First try at a simple GPSDO for the RaspberryPi. See here:
> http://www.c-c-i.com/exchange/for the file PiAutoTIC1.zip
Nice project Azelio! Here are a few comments after a cursory look at the VHDL:
- Gated clocks (i.e. LSClock) are in
Thanks for all the comments about this topic. They are much appreciated.
About the difficulty of measuring every cycle with a conventional
counter... thanks for that info, seems that i´ll have to make my own
measurement hardware. I liked the idea of a time stamping counter
it´s very doabl
The 24bit counter counts up to 999 then is reset to 0 to get a PPS out
of a 10MHz clock. The most significant bit is high from 0x80 to
0x98967F, so that you have a 161.1392ms wide high pulse when driving the
PPS output with the MSB.
On Thu, Feb 28, 2013 at 1:28 PM, Herbert Poetzl wrote:
>
On Thu, Feb 28, 2013 at 01:26:17AM +0100, Azelio Boriani wrote:
> First try at a simple GPSDO for the RaspberryPi. See here:
> http://www.c-c-i.com/exchange/ for the file PiAutoTIC1.zip
> Thanks to Bob Smither for his file exchange site.
Pardon my ignorance, but where does the 161ms PPS length
com
On Thu, Feb 28, 2013 at 03:49:55AM +0100, Magnus Danielson wrote:
> On 02/18/2013 10:32 PM, Herbert Poetzl wrote:
>> [ lot of stuff zapped ]
> It would be interesting if fractional resolution of the DDS
> would be developed using the PHASE interface.
> As PHASE ripples, a carry needs to be sent
Something I saw in John Miles recent post on the TB thread leads me to ask if a
regular TB can be upgraded to TB-E level firmaware, and if so is sensible to do
so?
Thanks
Dave
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