Azelio wrote:
Since I have not found a strong definition for the FLL, I assumed: if
PLL= zero phase error (and so zero frequency error) the FLL= same
frequency, random phase. The XOR with RC is a perfect fit for this:
same frequency all the time but phase determined by the EFC needed to
have tha
Hi
At the most basic level:
FLL is frequency locked. Consider a lock system driven by an FM discriminator.
(That’s
how the idea originally was done.) The output of the detector is a voltage
proportional to the
frequency error. With a simple loop (gain only / no integrator) you have a
static
http://www.megapathdsl.net/~hmurray/time-nuts/GPSDO/JAM-KS-2015-Aug-26.png
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Hi
It would be really interesting to eventually dig up a spec on just what these
two
boxes are supposed to do. There are far to many “interesting features” for them
all to have been un-intentional.
Bob
> On Aug 27, 2015, at 5:41 AM, Hal Murray wrote:
>
> More testing...
> I lost everything
Attila,
I concur with you, what Azelio described is a standard off the shelf PLL.
An XOR for a Type I phase discriminator, characterized by a 90 degree phase
lock, and with more complicated logic, a Type II PLL which locks at zero
degrees. In a well designed loop, in both cases over the long term
Since I have not found a strong definition for the FLL, I assumed: if
PLL= zero phase error (and so zero frequency error) the FLL= same
frequency, random phase. The XOR with RC is a perfect fit for this:
same frequency all the time but phase determined by the EFC needed to
have that frequency. The
it is a bit more complicated FLL need circuit which is sensitive to
frequency difference, it looks always, PLL need a phase detector and
has a capture range, which is depend mainly on the bandwidth of the loop
filter
there are combined phase /frequency detectors, which are sequential
circuits
Hi
> On Aug 27, 2015, at 3:58 AM, Hal Murray wrote:
>
>
> kb...@n1k.org said:
>>> Is there anything fundamental about SC that forces the turn over
> temperature
>>> to be high?
>
>> Simple answer yes. More complicated answer : that depends.
>
>> The crystal curve on an AT or an IT centers ro
Hi
> On Aug 26, 2015, at 11:54 PM, Bob Benward wrote:
>
> So how does a frequency lock work? How is it implemented? Can someone sketch
> a schematic?
>
> And what equipment or technique is used to measure a 2hz error at 100GHz?
As with all things, this is a “that depends" sort of thing. You
Tim wrote:
Many hobbyist GPSDO's work, by counting OCXO cycles between some number of
GPS PPS assertions.
Software adjusts EFC based on frequency count. Often times the frequency
count used as input to the software has not just random +/- 1 bobble in
last digit, but also an extra count or two i
On Thu, 27 Aug 2015 17:19:34 +0200
Azelio Boriani wrote:
> The simplest form of a frequency locked loop is the XOR gate, when the
> driving signals are 50% square waves. To achieve lock, the phase
> difference will be proportional to the voltage needed to the VCO to
> generate the desired frequen
The simplest form of a frequency locked loop is the XOR gate, when the
driving signals are 50% square waves. To achieve lock, the phase
difference will be proportional to the voltage needed to the VCO to
generate the desired frequency. Start with a 5V digital gate, suppose
your VCO needs 2.5V to be
Hi all the HP5065A owner.
I thought it was very interesting to have a list of existing HP5065A in the
world.
In particular, it would be nice to see where is situated the old and the new
still operating. I prepared then a list with some information such as serial
number, options etc. .
If you
Look in the manual for the 8640B as they use FLL there when the lock button is
pushed on the front panel. Simply, in one case, in lock, the numbers driving
the frequency readout is saved and then when the oscillator drifts one way or
the other, an EFC is applied that attempts to make the new rea
Many hobbyist GPSDO's work, by counting OCXO cycles between some number of
GPS PPS assertions.
Software adjusts EFC based on frequency count. Often times the frequency
count used as input to the software has not just random +/- 1 bobble in
last digit, but also an extra count or two in last digit d
More testing...
I lost everything from roughly 12:00-24:00 UTC Tue and 10:00-20:00 UTC Wed
I stumbled into an interesting quirk in the KS-24361.
Short version:
After it has been in holdover for 5 or 6 minutes, the GPS unit switches to
tracking the non-GPS unit and says it isn't in holdover
Hi,
I would like to receive some feedback on the Wavecrest 2079 using Timelab.
The main question is: can someone send me some outputs related to the noise
floor of the Wavecrest?
I would like to be reassured that, as written in the manual, the function
double(:meas:data) get the equivalent
So how does a frequency lock work? How is it implemented? Can someone sketch a
schematic?
And what equipment or technique is used to measure a 2hz error at 100GHz?
Bob
>>> -Original Message-
>>> From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Tim
>>> Shoppa
>>> Sent: W
kb...@n1k.org said:
>> Is there anything fundamental about SC that forces the turn over
temperature
>> to be high?
> Simple answer yes. More complicated answer : that depends.
> The crystal curve on an AT or an IT centers roughly at room temperature.
> When you fiddle the angles to get a stres
You might start with Leeson's equation to calculate the resonator Q that you
need to get the phase noise you desire. Overtone resonators have higher Q,
but they are too "stiff" to keep on frequency (with a reactive tuning
network) under conditions in which the resonator is exposed to any practical
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