ere are
> >> lots of logic gate chips out there that will run from 3.3 and
> >> accept 5V inputs. Use something reasonably fast and it will do a
> >> pretty good job.
> >>
> >> Bob
> >>
> >> On Sep 30, 2014, at 10:11 PM, Mark A. Haun
>
Hi Bob,
The OCXO is one of those 26-MHz ebay Pletronics from a couple years
back. I would like to not degrade its close-in phase noise (quoted as
-100 dBc @ 10 Hz, -130 dBc @ 100 Hz). Thinking about Said's suggestion
to phase lock a higher-frequency sampling clock to this, with a loop BW
somewhe
en
> further by using the ocxo to supress the vcxo PN.
>
> Welcome to our world, if you look at the archives there are 10++
> years of discussions about exactly doing this...
>
> Bye,
> Said
>
>
>
> Sent from my iPad
>
> On Sep 27, 2014, at 21:01, "Mark A
In my quest to learn Verilog and get my hands dirty with
software-defined radio, I'm currently designing a direct-sampling
shortwave receiver. This uses an 80-MSPS ADC, which requires a
low-phase-noise oscillator, e.g. Crystek CVHD-950 or Abracon ABLNO. It
would be nice to have some provision for
