Thanks to everyone who replied. I probably should have explained that
I am familiar with the various options for logic level conversion.
It's how those options affect clock noise that I was fuzzy on. Bob's
summary definitely helped. SN74LVC1T45 looks to be the winner.
Regards,
Mark
On Thu, 2
Hi
It will indeed be better for phase noise to do away with the resistive divider
and get faster edges.
Of course there are indeed resistive dividers that don’t slow things down. It’s
unlikely that a divider with a 10 ohm output impedance is going to tack on to
the output of an OCXO.
———
Would it not be better for phase noise to use a logic gate with a fast
transition than a resistive divider that would be slower due to the load
capacitance?
David
On 10/1/14 7:09 AM, Bob Camp wrote:
Hi
Ok, so it’s not a super duper low phase noise OCXO. It’s also at a reasonably
high frequ
level conversion 5V -> 3.3V
If it were me, I'd avoid the active buffers since there is no need for them
when going from higher to lower voltage swings. The output of a
buffer/inverter is guaranteed to be at least a little less clean than what
you started with.
First, check to see if
If it were me, I'd avoid the active buffers since there is no need for them
when going from higher to lower voltage swings. The output of a
buffer/inverter is guaranteed to be at least a little less clean than what
you started with.
First, check to see if the "5V" output really is a 5V signal. I
good that
level translation should be.
Regards,
Vasco Soares
- Original Message -
From: "Hal Murray"
To: "Discussion of precise time and frequency measurement"
Cc:
Sent: Wednesday, October 01, 2014 4:10 AM
Subject: Re: [time-nuts] Clock level conversion
Hi
Ok, so it’s not a super duper low phase noise OCXO. It’s also at a reasonably
high frequency.
I’d just drive it into a 5V tolerant input and move on. There are lots of logic
gate chips out there that will run from 3.3 and accept 5V inputs. Use something
reasonably fast and it will do a pre
vesoa...@deea.isel.ipl.pt said:
> I would suggest some 3.3V logic (inverter) gate with 5V tolerant inputs
> from Little Logic TI portfolio. There are buffered and unbuffered gate
> available.
What's the advantage of a chip over a pair of resistors?
hau...@keteu.org said:
> I have seen a resisti
Hi Bob,
The OCXO is one of those 26-MHz ebay Pletronics from a couple years
back. I would like to not degrade its close-in phase noise (quoted as
-100 dBc @ 10 Hz, -130 dBc @ 100 Hz). Thinking about Said's suggestion
to phase lock a higher-frequency sampling clock to this, with a loop BW
somewhe
Mark,
Lots of good parts on this page:
http://www.onsemi.com/PowerSolutions/parametrics.do?id=648
But as others are pointing out - it depends
Regards,
John
On Tue, Sep 30, 2014 at 2:46 PM, Mark Haun wrote:
> Is there a "best" way to do this without adding phase noise? For example,
> a
I would suggest some 3.3V logic (inverter) gate with 5V tolerant inputs
from Little Logic TI portfolio. There are buffered and unbuffered gate
available.
Em 2014-09-30 22:46, Mark Haun escreveu:
Is there a "best" way to do this without adding phase noise? For
example, a
5V OCXO into an ADF4
Hi
How quiet does it need to be?
Put another way - how good is the OCXO?
What frequency are we talking about?
What is the phase noise “need” after you get to 3.3V (is there a system spec)?
Bob
On Sep 30, 2014, at 5:46 PM, Mark Haun wrote:
> Is there a "best" way to do this without adding p
Is there a "best" way to do this without adding phase noise? For example, a
5V OCXO into an ADF4002, or a 3.3V or even 1.8V logic input. Is a resistive
divider the way to go?
Mark
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