I modified my previous pinout image adding some more info (thanks to John
and Rex for their suggestions):
you can find them at the following addresses:
JPG format (1.4MB):
<
http://www.rhodiatoce.com/pics/time-nuts/FE-5680A/FE-5680A_annotated_001.jpg
>
Editable Adobe photoshop format (40MB):
<
htt
Thanks guys!
Updated Elio's picture with the additional info John provided.
Revised picture posted here...
http://www.xertech.net/FE5680A/FE-5680A_annotated_2.jpg
Let me know if I got anything wrong. Elio, feel free to update your
original if you want to keep control of it.
-Rex
On 2/1/2012
> http://www.rhodiatoce.com/pics/time-nuts/FE-5680A_annotated.jpg
Excellent work! I look forward to any further info.
Great picture with the pins and some parts labelled. By the way, if you
want you could add the frequencies going into and out of the Xilinx
XC9572XL CPLD part:
Pin 64: 60 MH
Nice pix
Thanks
On Wed, Feb 1, 2012 at 8:50 PM, Elio Corbolante wrote:
> The 15 pin connector (near crystal oscillator) is used for JTAG programming
> the XC8572XL (XC) and the PSD813F1V (PSD).
> According to my analysis the pinout is the following:
>
> 1) Vcc/+5V - goes to pin 5 of MAX882 volta
The 15 pin connector (near crystal oscillator) is used for JTAG programming
the XC8572XL (XC) and the PSD813F1V (PSD).
According to my analysis the pinout is the following:
1) Vcc/+5V - goes to pin 5 of MAX882 voltage regulator: its 3.3V output
powers XC and PSD
2) Ground (GND)
3) PSD pin PC6 (JTA