symmetry is better to look with spectrum analyzer, at good symmetry you
should not see second harmonic
73
KJ6UHN
Alex
On 10/6/2015 12:28 AM, ed breya wrote:
Problem solved - one missing connection was fixed, and it now runs
just fine. Symmetry looks good on a scope, and the toggle rate is
Problem solved - one missing connection was fixed, and it now runs just
fine. Symmetry looks good on a scope, and the toggle rate is plenty
enough. It runs OK to beyond 120 MHz input.
Ed
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After studying the various divide by 3 circuits, I decided to try
designing one that would be simpler in terms of package count, using
available ECL DIPs on-hand. Instead of the JK-FF version followed by
duty cycle-fixing circuitry, I opted for two 10131 dual D-FFs to provide
the state
I found I have some 10135 dual JK FFs on hand, so will try a version
based on JK, that needs no extra gates, with a 10116 triple line
receiver for I/O. If it turns out that symmetry is needed, I'll add a
10131 D FF, and the 10116 already provides both clock edges. Either way,
it should be
Thanks guys - good info. Some of these circuits must be the ones I've
seen before, and some are new to me, so I'll keep them too (until I lose
them again).
I'm not sure if I will need symmetry in the output, but it seems better
to have it for cleaning up if necessary. The resulting signal
I need to build an ECL divide by 3 circuit to run at about 50 MHz input.
I know there are lots of examples out there, but I vaguely recall years
ago I stumbled upon one or more that also provided more of a symmetrical
output nearly 50 percent duty factor, by using both input edges, or
IIRC one would use a divide by 4 circuit with the final output feeding back to
an exclusive-or gate through which the (square wave) source clock passes. The
ex-or effectively adds a clock edge to the divide by four, making it divide by
three. It also changes the effective clock edge, so the
I have rediscovered what I need, so no problem anymore. Ed
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Division by an odd factor requires clocking off both edges of the incoming
clock if you wish to achieve a 50% duty cycle output. So the output duty cycle
is affected by the duty cycle and response to the possibly different risetime
and falltime of the incoming clock. I would think that for the
e...@telight.com said:
> I need to build an ECL divide by 3 circuit to run at about 50 MHz input. I
> know there are lots of examples out there, but I vaguely recall years ago I
> stumbled upon one or more that also provided more of a symmetrical output
> nearly 50 percent duty factor, by
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