As a first submission to a collection of pathological PPS divider designs where the input clock to output delay is so large that its jitter and more particularly its tempco are significant I suggest that the following:
Input stage HEF4017 with 10V power supply clock to output delay 110 ns max at 25C subsequent 6 stages Motorola MC4017 with 10V power supply clock to output delay ~400ns max At 25C Total propagation delay from clock to output ~ 2.5us max, tempco ~10ns/K. This design will operate reliably with a 10MHz input up to about 50C when the worst case maximum input clock frequency for the first stage If the 2nd and subsequent stages are operated at 5V the propagation delay will increase to about 4.9us max, however the divider will still work reliably over a reasonable temperature range. Bruce _______________________________________________ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
