Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Understanding Oliver Collins Paper "Design of Low
Jitter Hard Limiters"
Once the gain stages enter saturation their noise contribution decreases
significantly in a well designed limiter stage.
The noise contri
On 08/24/2012 12:07 AM, Bob Camp wrote:
Hi
In general, saturated logic (TTL / CMOS) will do better than non-saturated (ECL
/ LVDS). Faster with saturated generally = better, provided it's silicon. Once
you go to high mobility semiconductors the 1/f noise picks up. Yes, you need a
quiet supply
Hi
In general, saturated logic (TTL / CMOS) will do better than non-saturated (ECL
/ LVDS). Faster with saturated generally = better, provided it's silicon. Once
you go to high mobility semiconductors the 1/f noise picks up. Yes, you need a
quiet supply. How quiet is going to depend on your edg
On Wed, 22 Aug 2012 19:00:10 -0700, Hal Murray
wrote:
>jmulc...@cox.net said:
>> The amount of jitter verses logic family is all over the place as well. Take
>> a look at an LS verses an HCT vs an S family and you will see what I mean.
>> Some of them are very nasty, and are not all created equal
jmulc...@cox.net said:
> The amount of jitter verses logic family is all over the place as well. Take
> a look at an LS verses an HCT vs an S family and you will see what I mean.
> Some of them are very nasty, and are not all created equally.
Is there any collection of hard data? How much does i
The amount of jitter verses logic family is all over the place as well.
Take a look at an LS verses an HCT vs an S family and you will see what I mean.
Some of them are very nasty, and are not all created equally.
Jerry
At 09:58 AM 8/22/2012, you wrote:
>I was not measuring cycle to cycle jitter
, or do we?
Yours
Raj
-Original Message-
From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf
Of Azelio Boriani
Sent: Wednesday, August 22, 2012 6:44 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Understanding Oliver Co
I was not measuring cycle to cycle jitter but the input to output
jitter of a TTL gate itself when used as part of a delay circuit. The
input circuit and input waveform to the gate are very similar to what
would be expected in a sine wave zero crossing detector.
Using a 7S11/7T11 in sequential sa
ussion of precise time and frequency measurement
Subject: Re: [time-nuts] Understanding Oliver Collins Paper "Design of Low
Jitter Hard Limiters"
According to
http://cp.literature.agilent.com/litweb/pdf/5989-8794EN.pdf
the real time sampling scope (like the TDS220 or TDS3012) can measu
-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On
Behalf Of Azelio Boriani
Sent: Wednesday, August 22, 2012 5:55 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Understanding Oliver Collins Paper "Design of Low
Jitter Hard Limiters"
In your o
According to
http://cp.literature.agilent.com/litweb/pdf/5989-8794EN.pdf
the real time sampling scope (like the TDS220 or TDS3012) can measure cycle
to cycle jitter directly, whereas the equivalent time sampling has only one
sample each trigger and a little delay on the sampling point for the nex
Do you mean with a 7404 hex inverter? I actually did something like
this recently while adding a 75ns pre-trigger pulse to an existing
fast rise pulse generator.
The pre-trigger pulse ended up having significant pattern dependant
jitter caused by the adjacent TTL divider chain modulating the supp
In your opinion, if I build a 7404 ZCD and a hard limiter one, can I see
the jitter difference on a simple 'scope (Tek TDS220 or TDS3012) or do I
need the Wavecrest SIA3000?
On Wed, Aug 22, 2012 at 1:37 AM, Bob Camp wrote:
> Hi
>
> Since the Collins approach "tunes" the system for a single frequ
Hi
Since the Collins approach "tunes" the system for a single frequency input
(more or less), the approach is probably not the best for a "many decades" sort
of frequency range. There are a number of things that he alludes to in the
paper, but does not directly address. The most obvious is the
Hi Raj,
welcome. Thank you for joining the group and thanks to Magnus for his
comment about the Collins' paper.
On Tue, Aug 21, 2012 at 11:51 PM, Magnus Danielson <
mag...@rubidium.dyndns.org> wrote:
> Hi Raj,
>
>
> On 08/21/2012 06:50 PM, raj_so...@agilent.com wrote:
>
>> Hello everyone,
>>
>> I
Hi Raj,
On 08/21/2012 06:50 PM, raj_so...@agilent.com wrote:
Hello everyone,
I am new to this forum.
It looks like a lively discussion on various topics.
A colleague of mine here at Agilent pointed me to this paper entitled "The Design of Low
Jitter Hard Limiters" by Oliver Collins. In Bruce
Of Rex
Sent: Tuesday, August 21, 2012 1:39 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Understanding Oliver Collins Paper "Design of Low
Jitter Hard Limiters"
On 8/21/2012 1:22 PM, David wrote:
> On Tue, 21 Aug 2012 10:50:43 -0600, wrot
On 8/21/2012 1:22 PM, David wrote:
On Tue, 21 Aug 2012 10:50:43 -0600, wrote:
Hello everyone,
I am new to this forum.
It looks like a lively discussion on various topics.
A colleague of mine here at Agilent pointed me to this paper entitled "The Design of Low
Jitter Hard Limiters" by Oliver
On Tue, 21 Aug 2012 10:50:43 -0600, wrote:
>Hello everyone,
>
>I am new to this forum.
>It looks like a lively discussion on various topics.
>
>A colleague of mine here at Agilent pointed me to this paper entitled "The
>Design of Low Jitter Hard Limiters" by Oliver Collins. In Bruce Griffith
Hello everyone,
I am new to this forum.
It looks like a lively discussion on various topics.
A colleague of mine here at Agilent pointed me to this paper entitled "The
Design of Low Jitter Hard Limiters" by Oliver Collins. In Bruce Griffiths'
precision time in frequency webpage, this paper
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