Hi Murray,
Why did you use such a large division factor - or any for that
matter? Could you not just have used a PLL with very long time
constant running at 10 MHz?
Peter
On 27 June 2010 20:14, Murray Greenman murray.green...@rakon.com wrote:
I have a design which locks a high
On Sun, 27 Jun 2010 20:59:51 -0400
Robert Benward rbenw...@verizon.net wrote:
All this talk about interpolation reminds me of a little neat chip by Analog
Devices, AD9500. It's programmable digital delay, bit, with lops resolution
with a loons full-scale range. I believe (from app notes)
Unfortunately, the AD9500 line is obsolete with no replacement. Which means
it will be quite soon not available anymore.
On-Semi makes a programmable delay: MC100EP195, 2.2 to 12.2 ns in 10 ps steps
There are a couple of other similar chips.
I have a design which locks a high performance 10MHz OCXO to a 10MHz
source which should work equally well with the LEA5, or any source of 5
or 10MHz.
I designed it for use with a distributed factory GPS reference which has
picked up noise, hum and phase modulation, in order to deliver a high
To: time-nuts@febo.com
Sent: Sunday, June 27, 2010 3:14 PM
Subject: [time-nuts] Yet another GPSDO - locking to 10MHz
I have a design which locks a high performance 10MHz OCXO to a 10MHz
source which should work equally well with the LEA5, or any source of 5
or 10MHz.
I designed
